[entropy_src] Fix handling of backpressure in the hardware pipeline #21799

This commit cleans up and documents the control signals for the main FIFOs of the pipeline including the esrng, esbit, postht, precon and esfinal FIFOs. Most of the changes simplify the code but don't alter the behavior of the design as the used FIFO primitives already implement the logic to not accept pushes when full internally. However, there are some important changes that are necessary: 1. The esrng FIFO handles no backpressure anymore. This wasn't spec compliant. 2. The sample drop point in case of backpressure is moved to after the health tests and the window counter controls are updated. This means in case of backpressure, samples are tested but they're not pushed into the postht FIFO (or the esbit FIFO in case of single-bit mode). The window timer doesn't increment to keep the number of samples ending up in the conditioner fixed, independent of backpressure. This is required by the spec. Signed-off-by: Pirmin Vogel <[email protected]>

This commit switches all instances of prim_fifo_sync to use hardened counters for the pointers. Signed-off-by: Pirmin Vogel <[email protected]>

This commit adds a 32-bit wide distribution FIFO of configurable depth. The FIFO is added between the postht FIFO, the observe FIFO, the bypass FIFO and the precon FIFO. Its main purpose is to buffer entropy bits while the conditioner is busy such that we don't have to drop entropy bits from the hardware pipeline. Dropping entropy bits is not a big issue per se as it's allowed by the spec (when done after the health tests and in a way such that number of samples going into the conditioner is fixed). Also, under normal operating conditions, noise source samples arrive at very low rate and dropping bits should not be needed. However, verifying that the `correct` entropy bits are dropped is hard and seems impossible for our current DV environment as it requires to very accurately model the hardware pipeline which is undesirable. Thus, the safest approach is to add this new distribution FIFO and tune its depth parameter to handle potential backpressure from the conditioner such that dropping bits is not necessary. Signed-off-by: Pirmin Vogel <[email protected]>

This is useful to reduce the backpressure in the pipeline as this leads to entropy bits being dropped eventually which the scoreboard cannot handle at the moment. Signed-off-by: Pirmin Vogel <[email protected]>

Now that the CS AES Halt interface is handled by the SHA3 core itself, the Sha3Quiesce / Sha3MsgDone states can be combined into one state. This helps reducing the latency of the conditioner and thus the backpressure onto the entropy pipeline. The main_stage_rdy_i input signal can be removed as this is identical to the sha3_state_vld_i input signal checked in Sha3Valid. At this point in the FSM, it is always asserted and doesn't need to be checked again. Signed-off-by: Pirmin Vogel <[email protected]>

Previously, the CS AES Halt interface was only active when the SHA3 engine was performing the final Process operation for which the main SM always acknowledges the completion with a done pulse. After fixing the interface to always be active when the SHA3 engine is actively processing data, the main SM only sends the done pulse for a minority of SHA3 operations. This can cause the enable delay module to block the re-enablement of the entropy pipeline after disabling as it keeps waiting for a done pulse that is never going to arrive. This commit fixes this issue by using the sha3_block_processed signal instead of the done pulse. This signal is sent by the SHA3 engine whenever the processing of a block finishes. Signed-off-by: Pirmin Vogel <[email protected]>

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[entropy_src] Fix handling of backpressure in the hardware pipeline #21799

[entropy_src] Fix handling of backpressure in the hardware pipeline #21799

Commits on Mar 6, 2024