[i2c] V2(S) checklist items

[hcallahan-lowrisc]

Description

Unimplemented Testpoints

• target_fifo_watermark [i2c,dv] I2C target mode fifo watermark tests #23142
• host_mode_config_perf [i2c,dv] I2C precise perf test #23543
• host_mode_clock_stretching [i2c,dv] I2C precise perf test #23543
• target_mode_tx_stretch_ctrl [i2c,dv] Target mode tx stretch ctrl test #23186
• target_mode_nack_generation [i2c,dv] Target mode nack generation directed tests #23192
• host_mode_halt_on_nak [i2c,dv] I2C Controller-Mode NACK modelling, mapping TP:host_mode_halt_on_nak #23940

Regression

https://reports.opentitan.org/hw/ip/i2c/dv/2024.05.10_04.25.29/report.html

• [i2c,dv] I2C regression fixes #23987
• A sampling of testpoints with low passrates. This is no-longer accurate for master, as it was observed on 10/05/24, but the same thresholds for V2 signoff still apply. The above PR should bring everything back up to the requisite level.
  • i2c_target_perf 0%
  • i2c_target_unexp_stop 8%
  • i2c_target_stress_all 12%

Cov

• FSM 83.3%

Open Issues (effort tracked against each issue)

Also see #21755 for previous discussion.

• [i2c,dv] Confirm monitor changes in #21765 are not hiding degenerate behaviour #23078
• [hw,i2c,dv] Add assertions for host mode sda/scl interference and unstable interrupts #17822 -> M7
• [i2c,dv] Confirm monitor changes in #21765 are not hiding degenerate behaviour #23078 This issue was split out from the following:
  • [i2c,dv] Re-think monitor DV for detecting S/Sr/P conditions #21887 -> M7
• [ci,i2c] Re-enable "i2c_host_eeprom_test" in CI #22347

Signoff Process (effort tracked against this issue)

#22108