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[csrng/dv] Adjust csrng_intr test to properly test sw/hw_cmd_ack_sts #22869

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vogelpi opened this issue Apr 28, 2024 · 1 comment · Fixed by #24204
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[csrng/dv] Adjust csrng_intr test to properly test sw/hw_cmd_ack_sts #22869

vogelpi opened this issue Apr 28, 2024 · 1 comment · Fixed by #24204
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Component:DV DV issue: testbench, test case, etc. IP:csrng Subsystem:Entropy entropy_src, csrng, or edn related issues

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@vogelpi
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vogelpi commented Apr 28, 2024

Description

With #21981, CSRNG gained support for properly triggering and signaling command errors back to EDN as well as the software instance. This is great. However, the csrng_intr test still tests the corresponding status register bits by forcing them. And there is TODO in the DV code referring to the original issue #16516

Now that CSRNG can actually signal these errors, the csrng_intr test should be reworked to properly trigger those errors instead of just forcing the corresponding status bits.

@vogelpi vogelpi added Component:DV DV issue: testbench, test case, etc. Subsystem:Entropy entropy_src, csrng, or edn related issues IP:csrng labels Apr 28, 2024
@vogelpi vogelpi added this to the Earlgrey-PROD.M5 milestone Apr 28, 2024
vogelpi added a commit to vogelpi/opentitan that referenced this issue Apr 28, 2024
lowRISC#21981 reworked the status signaling of CSRNG and
changed the definition of the ack_sts signal from 1-bit to a multi-bit
enum which broke the csrng_intr vseq trying to force the ack and ack_sts
signals. This commit gets the sequence working again until it's reworked
to properly test the error signaling without forcing signals.

This is related to lowRISC#22869.

Signed-off-by: Pirmin Vogel <[email protected]>
vogelpi added a commit that referenced this issue Apr 29, 2024
#21981 reworked the status signaling of CSRNG and
changed the definition of the ack_sts signal from 1-bit to a multi-bit
enum which broke the csrng_intr vseq trying to force the ack and ack_sts
signals. This commit gets the sequence working again until it's reworked
to properly test the error signaling without forcing signals.

This is related to #22869.

Signed-off-by: Pirmin Vogel <[email protected]>
@vogelpi
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vogelpi commented Jul 2, 2024

@h-filali investigated this. The scoreboard is disabled in this test so it would be quite some work to do all the checking properly. It would be doable if the checking was done right in the sequence but we agreed that there are more important things to take care of first.

I am thus moving this to M7 for the moment but raising the priority.

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Labels
Component:DV DV issue: testbench, test case, etc. IP:csrng Subsystem:Entropy entropy_src, csrng, or edn related issues
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