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[cryptotest] //sw/device/tests/crypto/cryptotest:ecdh_kat #22210
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@moidx: Could be a problem in OTBN or with the entropy complex (not sure if entropy is required) |
Likely related to #22209. |
After including the keymgr fix (see #22819 (comment)), the test now passes on silicon for
See the attached log: ecdh_kat.txt Thanks @nasahlpa ! We couldn't test |
Previously, the command register ready bit was only polled for the additional data when writing commands to the SW register of EDN. When writing commands to CSRNG instead, not polling the command ready bit could cause CSRNG to drop additional data provided by software while handling a hardware command. Once the hardware command was handled, the software instance would win arbitration and CSRNG would wait for software to provide the dropped additional data, thereby stalling the entire entropy complex. This would happen for example if a HW instance request would collide with a software request. Since the software command FIFO is only 2 entries deep, it can only be guaranteed to absorb 2 words if the software interface doesn't win arbitration immediately. This is related to lowRISC#22209 and lowRISC#22210. Signed-off-by: Pirmin Vogel <[email protected]>
Previously, the main SM state was only checked for the first command word but not for the additional data. Not checking the main SM state before writing the additional data could cause CSRNG to drop additional data provided by software while handling a hardware command. Once the hardware command was handled, the software instance would win arbitration and CSRNG would wait for software to provide the dropped additional data, thereby stalling the entire entropy complex. This would happen for example if a HW instance request would collide with a software request. Since the software command FIFO is only 2 entries deep, it can only be guaranteed to absorb 2 words if the software interface doesn't win arbitration immediately. This commit contains the ES / CSRNG v.1.0.0 specific version of lowRISC#23166. In addition, it adds some more comments to properly document the underlying hardware issue directly in the cryptolib implementation. This is related to lowRISC#22209 and lowRISC#22210. Signed-off-by: Pirmin Vogel <[email protected]>
Previously, the main SM state was only checked for the first command word but not for the additional data. Not checking the main SM state before writing the additional data could cause CSRNG to drop additional data provided by software while handling a hardware command. Once the hardware command was handled, the software instance would win arbitration and CSRNG would wait for software to provide the dropped additional data, thereby stalling the entire entropy complex. This would happen for example if a HW instance request would collide with a software request. Since the software command FIFO is only 2 entries deep, it can only be guaranteed to absorb 2 words if the software interface doesn't win arbitration immediately. This commit contains the ES / CSRNG v.1.0.0 specific version of #23166. In addition, it adds some more comments to properly document the underlying hardware issue directly in the cryptolib implementation. This is related to #22209 and #22210. Signed-off-by: Pirmin Vogel <[email protected]>
Previously, the command register ready bit was only polled for the additional data when writing commands to the SW register of EDN. When writing commands to CSRNG instead, not polling the command ready bit could cause CSRNG to drop additional data provided by software while handling a hardware command. Once the hardware command was handled, the software instance would win arbitration and CSRNG would wait for software to provide the dropped additional data, thereby stalling the entire entropy complex. This would happen for example if a HW instance request would collide with a software request. Since the software command FIFO is only 2 entries deep, it can only be guaranteed to absorb 2 words if the software interface doesn't win arbitration immediately. This is related to #22209 and #22210. Signed-off-by: Pirmin Vogel <[email protected]>
The two relevant PRs for this issue (for ES and PROD) have both been merged. I've extensively tested this on FPGA (using an |
Previously, the command register ready bit was only polled for the additional data when writing commands to the SW register of EDN. When writing commands to CSRNG instead, not polling the command ready bit could cause CSRNG to drop additional data provided by software while handling a hardware command. Once the hardware command was handled, the software instance would win arbitration and CSRNG would wait for software to provide the dropped additional data, thereby stalling the entire entropy complex. This would happen for example if a HW instance request would collide with a software request. Since the software command FIFO is only 2 entries deep, it can only be guaranteed to absorb 2 words if the software interface doesn't win arbitration immediately. This is related to lowRISC#22209 and lowRISC#22210. Signed-off-by: Pirmin Vogel <[email protected]>
Hierarchy of regression failure
Block level
Failure Description
Steps to Reproduce
earlgrey_es_sival
Should be reproducible with
sival
sku as well.Tests with similar or related failures
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