[uart] D2 Signoff

[msfschaffner]

Description

Ensure D2 signoff criteria are fulfilled after focus area changes have landed.

[GregAC]

Review Hash: 93fedf9

Commits since Earlgrey-ES tapeout

91b22bb [uart,dv] Fix loopback test when using CDC sync
51fc76c [uart] Speed up uart_intr test
6577de1 [uart,doc] uart watermark documentation update
fbe9bae [uart,dv] Fix uart TX watermark interrupt test
0576a09 [uart] Correct timeout comment units
0c580fa [uart] Further limit baud in uart_rx_oversample
8ea8f8f [uart,rtl,dv] Switch watermark interrupts to status type
61a237e [util/reggen] reverse order of substruct generation
de31bdf [reggen] Remove the devmode input
eccaba5 [doc] Updated Chromium EC URL
5d25eb8 [uart,sival] Add a feature list for the uart block
1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
59f8142 [doc] Moved badges over to using hosted images
3346485 [doc] uart registers and interfaces now use CMDGEN
7688e71 [reggen] Add initial support for version and cip_id hjson fields
fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
0ba10b3 [reggen] Add CIP_IDs and bump all major versions

Of these commits only one effects UART RTL specifically:

8ea8f8f [uart,rtl,dv] Switch watermark interrupts to status type

• Agreed RTL change for PROD switching tx_watermark and rx_watermark to be status type interrupts

Other commits that effect RTL are from general tooling and primitive changes
that effect multiple blocks.

Closed issues

• [hw,uart] noise filter issue with CDC instrumentation #18912
• [dv/cdc] Enable CDC instrumentation in all ips #16689
• [chip] Convert Edge-triggered status interrupt to Level #15378

Open issues

• [top_earlgrey] Area optimizations for production #22025
  • To be closed for D2, PR already open, [uart] Reduce TX FIFO depth from 128B to 32B #22026
• [dvsim] Questa uart_smoke failing at tl_agent_pkg load #21518
  • Questa related issue, not a D2 concern
• [dv,top_earlgrey] baudrate not configurable via configure_uart_agent #21188
  • DV environment issue, not a D2 concern
• [test-triage] uart_rx_oversample #18648
  • chip-level test failure, likely DV issue, not a D2 concern
• [test-triage] //sw/device/tests:uart_smoketest_signed_sim_verilator is broken #17813
  • chip-level test failure, likely SW issue, not a D2 concern
• [doc] Register style-guide #17348
  • generic doc issue, using UART as an example
• [uart] Convert edge based interrupt to level  #16693
  • Switching interrupts to status types, complete for tx_watermark/rx_watermark. Request for new true 'tx_empty' interrupt (current 'tx_empty' is more accurately 'tx_done'). Minor new feature, that's not essential and can be done post D2
• [dv] The #1ps delay in dut_init means we never start a sequence item on the first clock edge #10137
  • General DV environment issue effecting UART and other blocks, not a D2 concern
• Standardize all FIFOs in OpenTitan #7826
  • Enhancement to standardize how FIFOs work across all OpenTitan IPs, not being implement for PROD so not a D2 concern
• [all] interrupt consolidation #3421
  • Consolidate interrupts for various IPs (including UART) to reduce the total interrupt lines out of each IP, not being considered for PROD so not a D2 concern

Once PR: #22026 is merged I am happy UART fulfills D2 sign-off criteria.

[GregAC]

@msfschaffner PTAL

[msfschaffner]

This looks good to me. Specifically, the Hjson currently claims D3 v1.1.0:

opentitan/hw/ip/uart/data/uart.hjson

Lines 30 to 37 in 514aaa6

	{
	version: "1.1.0",
	life_stage: "L1",
	design_stage: "D3",
	verification_stage: "V2S",
	dif_stage: "S2",
	notes: ""
	}

I think I am fine with leaving at D3, but I think we may have to bump the version to v2.0.0 due to the CSR and IRQ changes.
WDYT?

[GregAC]

I think we need to move it to D2 given there's known post D2 RTL change (the 'proper' tx_empty interrupt). But yes can bump the version as well.

[msfschaffner]

Ah ok I oversaw that one - agreed and D2 sounds good to me. You could just go all the way to D2S actually, since this is not a security block and the bus integrity alert is connected.

[GregAC]

PR here to change version and design stage: #22167

[andreaskurth]

Closing as completed in #22167.