[bazel, dvsim] Convert dvsim-executed tests to the new rules #19797
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Description
opentitan_functesttoopentitan_test.new_rulesin the dvsim configuration file.Some of these tests will have to wait for the ROM rules in #19710 before they can be converted.
The following is a list of tests and their corresponding dvsim configuration files.
//sw/device/tests/autogen:alert_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/autogen:plic_all_irqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:adc_ctrl_sleep_debug_cable_wakeup_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:alert_handler_entropy_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:alert_handler_escalation_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:all_escalation_resets_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:ast_clk_rst_inputs:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:ast_usb_clk_calib:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:clkmgr_external_clk_src_for_lc_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:csrng_lc_hw_debug_en_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:entropy_src_fuse_en_fw_read_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:flash_ctrl_lc_rw_en_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:flash_init_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:flash_rma_unlocked_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:gpio_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:i2c_device_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:i2c_host_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:inject_scramble_seed:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_ctrl_program_error:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_ctrl_scrap_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_ctrl_transition_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_walkthrough_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pattgen_ios_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_b2b_sleep_reset_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_reset_reqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_wake_ups:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_reset_reqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_wake_ups:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_random_sleep_all_reset_reqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_random_sleep_all_wake_ups:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_sysrst_ctrl_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:pwrmgr_usbdev_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:rv_dm_access_after_wakeup:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:rv_dm_ndm_reset_req:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:rv_dm_ndm_reset_req_when_cpu_halted:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sensor_ctrl_status_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sleep_pin_mio_dio_val_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sleep_pin_retention_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sleep_pin_wake_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:spi_device_tpm_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:spi_host_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:spi_passthrough_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:spi_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_ec_rst_l_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_in_irq_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_inputs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_outputs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_reset_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:sysrst_ctrl_ulp_z3_wakeup_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests/sim_dv:uart_tx_rx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aes_entropy_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aes_idle_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aes_masking_off_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:alert_handler_lpg_clkoff_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:alert_handler_lpg_reset_toggle_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:alert_handler_ping_timeout_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aon_timer_irq_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aon_timer_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:aon_timer_wdog_bite_reset_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:aon_timer_wdog_lc_escalate_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:ast_clk_outs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:chip_power_idle_load:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:chip_power_sleep_load:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_jitter_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_off_aes_trans_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_off_hmac_trans_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_off_kmac_trans_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_off_otbn_trans_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_off_peri_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_reset_frequency_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_sleep_frequency_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:clkmgr_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:csrng_edn_concurrency_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:csrng_kat_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:csrng_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:entropy_src_ast_rng_req_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:entropy_src_csrng_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:entropy_src_edn_reqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:entropy_src_kat_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:entropy_src_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:example_concurrency_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:example_test_from_flash:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:example_test_from_rom:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:flash_ctrl_clock_freqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:flash_ctrl_idle_low_power_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:flash_ctrl_ops_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:flash_ctrl_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:flash_scrambling_smoketest:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:gpio_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:hmac_enc_idle_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:hmac_enc_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:hmac_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:keymgr_key_derivation_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:keymgr_sideload_aes_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:keymgr_sideload_kmac_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:keymgr_sideload_otbn_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_app_rom_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_entropy_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_idle_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_mode_cshake_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_mode_kmac_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:kmac_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:lc_ctrl_otp_hw_cfg_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:otbn_ecdsa_op_irq_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:otbn_mem_scramble_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:otbn_randomness_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:otbn_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:otp_ctrl_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:plic_sw_irq_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:pwrmgr_sleep_disabled_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:pwrmgr_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:pwrmgr_usb_clk_disabled_when_active_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:pwrmgr_wdog_reset_reqs_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rstmgr_alert_info_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rstmgr_cpu_info_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rstmgr_smoketest:hw/top_earlgrey/dv/chip_sim_cfg.hjson,hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:rstmgr_sw_req_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rstmgr_sw_rst_ctrl_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rv_core_ibex_address_translation_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rv_core_ibex_icache_invalidate_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rv_core_ibex_nmi_irq_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rv_core_ibex_rnd_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:rv_plic_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:rv_timer_smoketest:hw/top_earlgrey/dv/chip_sim_cfg.hjson,hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:sensor_ctrl_alert_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:sensor_ctrl_wakeup_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:sleep_pwm_pulses_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:sram_ctrl_sleep_sram_ret_contents_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:sram_ctrl_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:uart_smoketest:hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/tests:uart_smoketest_signed:hw/top_earlgrey/dv/chip_rom_tests.hjson//sw/device/tests:usbdev_pincfg_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:usbdev_pullup_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:usbdev_setuprx_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:usbdev_stream_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:usbdev_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:usbdev_vbus_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/tests:power_virus_systemtest:hw/top_earlgrey/dv/chip_sim_cfg.hjson//third_party/coremark/top_earlgrey:coremark_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson@manufacturer_test_hooks//:example_test:hw/top_earlgrey/dv/chip_sim_cfg.hjson//sw/device/silicon_creator/lib/drivers:keymgr_functest:hw/top_earlgrey/dv/chip_rom_tests.hjson//sw/device/tests:aes_smoketest:hw/top_earlgrey/dv/chip_sim_cfg.hjson,hw/top_earlgrey/dv/chip_smoketests.hjson//sw/device/silicon_creator/rom/e2e:rom_e2e_shutdown_exception_c:hw/top_earlgrey/dv/chip_rom_tests.hjson//sw/device/silicon_creator/rom/e2e:rom_e2e_static_critical:hw/top_earlgrey/dv/chip_rom_tests.hjsonThe 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