[chip-test] yes

[Adam11072000]

Test point name

aes

Host side component

None

OpenTitanTool infrastructure implemented

None

Contact person

No response

Checklist

we added another aes module to check for fault injections, i.e we compare the result between our ads core and the result of the current aes core, and if it's not the same, we raise an alert.
we simulated the aes as a standalone via Verilator, it works, the signals make sense, and the alert works too.
now we want to start chip-level testing via dvsim
the tests fail, we fail at line 252 in aes.sv, asserting that edn_o should have a value after reset.
our module is present in aes_core, thus it's not related to end_o.
first question:
any idea how we could get waves and how does vcs dump them using ./util/dvsim/dvsim.py hw/ip/aes/dv/aes_no_masking_sim_cfg.hjson --tool vis --waves fsdb?
2nd question:
why does it fail if we did not change the outer layer and only the inner logic of comparing?
the outputs of aes_core.sv did not change after our module (we disabled the alerts from our module, thus all the outputs are still the same)
thanks

[Adam11072000]

Actually tests now passed, our branch was out of sync from the main branch, pull rebase solved it.
Now just need to know how to dump waves and open them.
Thanks

[msfschaffner]

Hi @Adam11072000

The command you are running should dump an fsdb file into the working directory of the simulation (typically somewhere under ./scratch/<branch name>/<testbench name>/<seed.testname>). If you have verdi, you can open that with verdi -ssf <path to fsdb file>.

Alternatively you can also use Xcelium and dump an shm file that you can then open with SimVision.

[vogelpi]

This seems to be a duplicate of #17696. Closing.