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[chip-test] AES + Verilator tooling question #17696

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Adam11072000 opened this issue Mar 25, 2023 · 5 comments
Closed

[chip-test] AES + Verilator tooling question #17696

Adam11072000 opened this issue Mar 25, 2023 · 5 comments
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Component:ChipLevelTest Used to filter the chip-level test backlog Type:Question Questions

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@Adam11072000
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Test point name

chip_sim_cfg

Host side component

None

OpenTitanTool infrastructure implemented

Unknown

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Hello,

We added a smaller AES ip inside aes_core.sv for redundancy approach against fault injections.
we simulated aes IP using fusesoc and verilator and we verified that it works.
now we need to start chip-level testing to validate that we did not brick anything.
we are running this command :
fusesoc --cores-root=. run --setup --tool verilator --build lowrisc:dv:chip_sim:0.1

and we're getting this output:
ERROR: %Error-UNSUPPORTED: ../src/lowrisc_dv_str_utils_0/str_utils_pkg.sv:109:14: Unsupported: empty queues ("{ }")
109 | result = {};
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.210
%Error: ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:9:12: Cannot find include file: uvm_macros.svh
9 | include "uvm_macros.svh" | ^~~~~~~~~~~~~~~~ ... Looked in: ../src/lowrisc_dv_crypto_prince_ref_0.1/uvm_macros.svh ../src/lowrisc_dv_crypto_prince_ref_0.1/uvm_macros.svh.v ../src/lowrisc_dv_crypto_prince_ref_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/detail/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/detail/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/detail/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/mixin/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/mixin/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/mixin/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/constants/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/constants/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/constants/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/detail/uvm_macros.svh.sv ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/uvm_macros.svh ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/uvm_macros.svh.v ../src/lowrisc_dv_digestpp_dpi_0.1/vendor/kerukuro_digestpp/algorithm/uvm_macros.svh.sv ../src/lowrisc_dv_dv_fcov_macros_0/uvm_macros.svh ../src/lowrisc_dv_dv_fcov_macros_0/uvm_macros.svh.v ../src/lowrisc_dv_dv_fcov_macros_0/uvm_macros.svh.sv ../src/lowrisc_dv_dv_macros_0/uvm_macros.svh ../src/lowrisc_dv_dv_macros_0/uvm_macros.svh.v ../src/lowrisc_dv_dv_macros_0/uvm_macros.svh.sv ../src/lowrisc_dv_secded_enc_0/uvm_macros.svh ../src/lowrisc_dv_secded_enc_0/uvm_macros.svh.v ../src/lowrisc_dv_secded_enc_0/uvm_macros.svh.sv ../src/lowrisc_model_aes_1.0/uvm_macros.svh ../src/lowrisc_model_aes_1.0/uvm_macros.svh.v ../src/lowrisc_model_aes_1.0/uvm_macros.svh.sv ../src/lowrisc_prim_util_get_scramble_params_0/rtl/uvm_macros.svh ../src/lowrisc_prim_util_get_scramble_params_0/rtl/uvm_macros.svh.v ../src/lowrisc_prim_util_get_scramble_params_0/rtl/uvm_macros.svh.sv ../src/lowrisc_prim_util_memload_0/rtl/uvm_macros.svh ../src/lowrisc_prim_util_memload_0/rtl/uvm_macros.svh.v ../src/lowrisc_prim_util_memload_0/rtl/uvm_macros.svh.sv ../src/lowrisc_dv_scramble_model_0/uvm_macros.svh ../src/lowrisc_dv_scramble_model_0/uvm_macros.svh.v ../src/lowrisc_dv_scramble_model_0/uvm_macros.svh.sv ../src/lowrisc_dv_verilator_memutil_dpi_0/cpp/uvm_macros.svh ../src/lowrisc_dv_verilator_memutil_dpi_0/cpp/uvm_macros.svh.v ../src/lowrisc_dv_verilator_memutil_dpi_0/cpp/uvm_macros.svh.sv ../src/lowrisc_dv_mem_model_0/uvm_macros.svh ../src/lowrisc_dv_mem_model_0/uvm_macros.svh.v ../src/lowrisc_dv_mem_model_0/uvm_macros.svh.sv ../src/lowrisc_dv_verilator_memutil_dpi_scrambled_0/cpp/uvm_macros.svh ../src/lowrisc_dv_verilator_memutil_dpi_scrambled_0/cpp/uvm_macros.svh.v ../src/lowrisc_dv_verilator_memutil_dpi_scrambled_0/cpp/uvm_macros.svh.sv ../src/lowrisc_prim_assert_0.1/rtl/uvm_macros.svh ../src/lowrisc_prim_assert_0.1/rtl/uvm_macros.svh.v ../src/lowrisc_prim_assert_0.1/rtl/uvm_macros.svh.sv ../src/lowrisc_dv_dv_utils_0/uvm_macros.svh ../src/lowrisc_dv_dv_utils_0/uvm_macros.svh.v ../src/lowrisc_dv_dv_utils_0/uvm_macros.svh.sv ../src/lowrisc_ibex_ibex_core_0.1/rtl/uvm_macros.svh ../src/lowrisc_ibex_ibex_core_0.1/rtl/uvm_macros.svh.v ../src/lowrisc_ibex_ibex_core_0.1/rtl/uvm_macros.svh.sv ../src/lowrisc_dv_dv_base_reg_0/uvm_macros.svh ../src/lowrisc_dv_dv_base_reg_0/uvm_macros.svh.v ../src/lowrisc_dv_dv_base_reg_0/uvm_macros.svh.sv ../src/lowrisc_dv_csr_utils_0/uvm_macros.svh ../src/lowrisc_dv_csr_utils_0/uvm_macros.svh.v ../src/lowrisc_dv_csr_utils_0/uvm_macros.svh.sv ../src/lowrisc_dv_dv_lib_0/uvm_macros.svh ../src/lowrisc_dv_dv_lib_0/uvm_macros.svh.v ../src/lowrisc_dv_dv_lib_0/uvm_macros.svh.sv ../src/lowrisc_dv_i2c_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_i2c_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_i2c_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_i2c_agent_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_i2c_agent_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_i2c_agent_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_jtag_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_jtag_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_jtag_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_pattgen_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_pattgen_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_pattgen_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_push_pull_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_push_pull_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_push_pull_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_push_pull_agent_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_push_pull_agent_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_push_pull_agent_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_pwm_monitor_0.1/uvm_macros.svh ../src/lowrisc_dv_pwm_monitor_0.1/uvm_macros.svh.v ../src/lowrisc_dv_pwm_monitor_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_scoreboard_0/uvm_macros.svh ../src/lowrisc_dv_scoreboard_0/uvm_macros.svh.v ../src/lowrisc_dv_scoreboard_0/uvm_macros.svh.sv ../src/lowrisc_dv_sec_cm_0/uvm_macros.svh ../src/lowrisc_dv_sec_cm_0/uvm_macros.svh.v ../src/lowrisc_dv_sec_cm_0/uvm_macros.svh.sv ../src/lowrisc_dv_spi_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_spi_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_spi_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_spi_agent_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_spi_agent_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_spi_agent_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_tl_agent_0/uvm_macros.svh ../src/lowrisc_dv_tl_agent_0/uvm_macros.svh.v ../src/lowrisc_dv_tl_agent_0/uvm_macros.svh.sv ../src/lowrisc_dv_tl_agent_0/seq_lib/uvm_macros.svh ../src/lowrisc_dv_tl_agent_0/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_tl_agent_0/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_uart_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_uart_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_uart_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_uart_agent_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_uart_agent_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_uart_agent_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_alert_esc_agent_0/uvm_macros.svh ../src/lowrisc_dv_alert_esc_agent_0/uvm_macros.svh.v ../src/lowrisc_dv_alert_esc_agent_0/uvm_macros.svh.sv ../src/lowrisc_dv_alert_esc_agent_0/seq_lib/uvm_macros.svh ../src/lowrisc_dv_alert_esc_agent_0/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_alert_esc_agent_0/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_jtag_dmi_agent_0/uvm_macros.svh ../src/lowrisc_dv_jtag_dmi_agent_0/uvm_macros.svh.v ../src/lowrisc_dv_jtag_dmi_agent_0/uvm_macros.svh.sv ../src/lowrisc_dv_jtag_riscv_agent_0.1/uvm_macros.svh ../src/lowrisc_dv_jtag_riscv_agent_0.1/uvm_macros.svh.v ../src/lowrisc_dv_jtag_riscv_agent_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_jtag_riscv_agent_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_jtag_riscv_agent_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_jtag_riscv_agent_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_cip_lib_0/uvm_macros.svh ../src/lowrisc_dv_cip_lib_0/uvm_macros.svh.v ../src/lowrisc_dv_cip_lib_0/uvm_macros.svh.sv ../src/lowrisc_dv_cip_lib_0/seq_lib/uvm_macros.svh ../src/lowrisc_dv_cip_lib_0/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_cip_lib_0/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_aes_model_dpi_0/uvm_macros.svh ../src/lowrisc_dv_aes_model_dpi_0/uvm_macros.svh.v ../src/lowrisc_dv_aes_model_dpi_0/uvm_macros.svh.sv ../src/lowrisc_dv_xbar_env_0.1/uvm_macros.svh ../src/lowrisc_dv_xbar_env_0.1/uvm_macros.svh.v ../src/lowrisc_dv_xbar_env_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_xbar_env_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_xbar_env_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_xbar_env_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_ip_rv_core_ibex_0.1/rtl/uvm_macros.svh ../src/lowrisc_ip_rv_core_ibex_0.1/rtl/uvm_macros.svh.v ../src/lowrisc_ip_rv_core_ibex_0.1/rtl/uvm_macros.svh.sv ../src/lowrisc_dv_mem_bkdr_util_0/uvm_macros.svh ../src/lowrisc_dv_mem_bkdr_util_0/uvm_macros.svh.v ../src/lowrisc_dv_mem_bkdr_util_0/uvm_macros.svh.sv ../src/lowrisc_dv_xbar_test_0.1/uvm_macros.svh ../src/lowrisc_dv_xbar_test_0.1/uvm_macros.svh.v ../src/lowrisc_dv_xbar_test_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_chip_env_0.1/uvm_macros.svh ../src/lowrisc_dv_chip_env_0.1/uvm_macros.svh.v ../src/lowrisc_dv_chip_env_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_chip_env_0.1/seq_lib/uvm_macros.svh ../src/lowrisc_dv_chip_env_0.1/seq_lib/uvm_macros.svh.v ../src/lowrisc_dv_chip_env_0.1/seq_lib/uvm_macros.svh.sv ../src/lowrisc_dv_chip_env_0.1/autogen/uvm_macros.svh ../src/lowrisc_dv_chip_env_0.1/autogen/uvm_macros.svh.v ../src/lowrisc_dv_chip_env_0.1/autogen/uvm_macros.svh.sv ../src/lowrisc_dv_chip_test_0.1/uvm_macros.svh ../src/lowrisc_dv_chip_test_0.1/uvm_macros.svh.v ../src/lowrisc_dv_chip_test_0.1/uvm_macros.svh.sv ../src/lowrisc_dv_chip_sim_0.1/tb/uvm_macros.svh ../src/lowrisc_dv_chip_sim_0.1/tb/uvm_macros.svh.v ../src/lowrisc_dv_chip_sim_0.1/tb/uvm_macros.svh.sv ../src/lowrisc_dv_chip_sim_0.1/autogen/uvm_macros.svh ../src/lowrisc_dv_chip_sim_0.1/autogen/uvm_macros.svh.v ../src/lowrisc_dv_chip_sim_0.1/autogen/uvm_macros.svh.sv uvm_macros.svh uvm_macros.svh.v uvm_macros.svh.sv %Error-PKGNODECL: ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:10: Package/class 'uvm_pkg' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | import uvm_pkg::*; | ^~~~~~~ %Error: ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:10: Importing from missing package 'uvm_pkg' 7 | import uvm_pkg::*; | ^~~~~~~ %Error-UNSUPPORTED: ../src/lowrisc_dv_mem_model_0/mem_model.sv:8:44: Unsupported: class parameters 8 | localparam int MaskWidth = DataWidth / 8; | ^ ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv %Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:16:3: Define or directive not defined: 'uvm_object_param_utils'
16 | uvm_object_param_utils(mem_model#(AddrWidth, DataWidth)) | ^~~~~~~~~~~~~~~~~~~~~~~ ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv %Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:16:26: syntax error, unexpected '(' 16 | uvm_object_param_utils(mem_model#(AddrWidth, DataWidth))
| ^
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:30:5: syntax error, unexpected if
30 | if (addr_exists(addr)) begin
| ^~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:32:7: Define or directive not defined: 'uvm_info' : ... Suggested alternative: 'dv_info'
32 | uvm_info($sformatf("%m"), $sformatf("Read Mem : Addr[0x%0h], Data[0x%0h]", addr, data), UVM_HIGH) | ^~~~~~~~~ ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv %Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:35:7: Define or directive not defined: 'uvm_error'
: ... Suggested alternative: 'dv_error' 35 | uvm_error($sformatf("%m"), $sformatf("read from uninitialized addr 0x%0h", addr))
| ^~~~~~~~~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:41:4: Define or directive not defined: 'uvm_info' : ... Suggested alternative: 'dv_info'
41 | uvm_info($sformatf("%m"), $sformatf("Write Mem : Addr[0x%0h], Data[0x%0h]", addr, data), UVM_HIGH) | ^~~~~~~~~ ../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv %Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:46:4: Define or directive not defined: 'uvm_info'
: ... Suggested alternative: 'dv_info' 46 | uvm_info($sformatf("%m"), $sformatf("Compare Mem : Addr[0x%0h], Act Data[0x%0h], Exp Data[0x%0h]",
| ^~~~~~~~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:54:5: syntax error, unexpected for
54 | for (int i = 0; i < DataWidth / 8; i++) begin
| ^~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:66:5: syntax error, unexpected for
66 | for (int i = DataWidth / 8 - 1; i >= 0; i--) begin
| ^~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:78:5: syntax error, unexpected for
78 | for (int i = 0; i < DataWidth / 8; i++) begin
| ^~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: ../src/lowrisc_dv_mem_model_0/mem_model.sv:85:11: Define or directive not defined: 'uvm_error' : ... Suggested alternative: 'dv_error'
85 | `uvm_error($sformatf("%m"), $sformatf("address 0x%0x not exists", byte_addr))
| ^~~~~~~~~~
../src/lowrisc_dv_mem_model_0/mem_model_pkg.sv:7:20: ... note: In file included from mem_model_pkg.sv
%Error: Cannot continue
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make: *** [Makefile:16: Vtb.mk] Error 1

ERROR: Failed to build lowrisc:dv:chip_sim:0.1 : '['make']' exited with an error: 2

this is the output on the original REPO without our changes. the same output is also when we add our changes.
how do we simulation tests?

thanks

@Adam11072000 Adam11072000 added the Component:ChipLevelTest Used to filter the chip-level test backlog label Mar 25, 2023
@Adam11072000
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i found another way to run the tests, but it still won't work
here is the command:

adamgdbn@Adam-computer:~/Desktop/opentitan$ ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i smoke --tool verilator --verbose=debug
INFO: [dvsim] [proj_root]: /home/adamgdbn/Desktop/opentitan
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/top_earlgrey/dv/chip_sim_cfg.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/top_earlgrey/dv/chip_rom_tests.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/top_earlgrey/dv/chip_smoketests.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/ip/tlul/generic_dv/xbar_tests.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/dv/tools/dvsim/tests/csr_tests.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/ip/aes/model/aes_model_sim_opts.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/dv/tools/dvsim/common_sim_cfg.hjson
DEBUG: [utils] Parsing /home/adamgdbn/Desktop/opentitan/hw/dv/tools/dvsim/verilator.hjson
ERROR: [CfgFactory] '/home/adamgdbn/Desktop/opentitan/hw/dv/tools/dvsim/verilator.hjson': Value for key 'run_dir' is '{scratch_path}/{run_dir_name}/out', but we already had a conflicting value of '{scratch_path}/{run_dir_name}/latest'.

@cindychip
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Thank you for reporting this issue. Currently our DV testbench mainly support VCS and Xcelium.

@Adam11072000
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Adam11072000 commented Apr 7, 2023

any way then to get traces from simulation via bazel?
tests via bazel that use verilator actually work

@a-will
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a-will commented Apr 24, 2023

These tests are UVM-based, which verilator does not currently support.

For tests that do support verilator, you can append the argument --test_arg --verilator-args=--trace to your bazel test command. The sim.fst file will appear somewhere in bazel-bin/<path-to-test.runfiles>/ (generally, the working directory of the test when bazel executes it).

@johngt johngt added the Type:Question Questions label May 8, 2023
@johngt johngt changed the title [chip-test] [chip-test] AES + Verilator tooling question May 8, 2023
@moidx moidx added this to the Community Support milestone May 11, 2023
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vogelpi commented Jul 21, 2023

I am closing this issue as the question on how to get AES waves from the Verilator top-level testbench has been answered and there hasn't been any activity for quite some time now. Feel free to re-open if you don't agree.

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