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[dv/clkmgr] Test different rst_io* and rst_root_io* #17934

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matutem opened this issue Apr 11, 2023 · 3 comments
Open

[dv/clkmgr] Test different rst_io* and rst_root_io* #17934

matutem opened this issue Apr 11, 2023 · 3 comments
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Component:DV DV issue: testbench, test case, etc. Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones IP:clkmgr Priority:P2 Priority: medium
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@matutem
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matutem commented Apr 11, 2023

Description

clkmgr has rst_io_ni, rst_io_div2_ni, and rst_io_div4_ni. Similarly it has three rst_root_io*. The testbench hooks them all to the same interface.

We should hook these to different interfaces and create simple tests that send different stimuli to each in order to verify they behave as expected.

This seems like a low priority test since the functional differences between them are pretty simple.

@matutem matutem added the Component:DV DV issue: testbench, test case, etc. label Apr 11, 2023
@matutem matutem added this to the Discrete: M2.5.Backlog milestone Apr 11, 2023
@matutem matutem self-assigned this Apr 11, 2023
@matutem matutem added Priority:P2 Priority: medium IP:clkmgr labels Apr 11, 2023
@msfschaffner msfschaffner added the Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones label Oct 7, 2023
@andreaskurth
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We should check whether rstmgr releases all of those at the same time -- if it does, we can defer this to future release

@matutem
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matutem commented May 11, 2024

They are by rstmgr released at slightly different times. All the corresponding clocks must be running, and the parent reset is sync'ed to the corresponding clock, so they are off by a 0 through 3 cycles of the 96 MHz io clock.

  • The parent reset of the rst_por_* resets is rst_por_aon_n[DomainAonSel]
  • The parent reset of all rst_lc_* resets is rst_lc_src_n[DomainAonSel]

The rstmgr rst_por_* resets are named rst_root_* in clkmgr:

  • rst_root_io_n resets both clock dividers, so the divided clocks are pretty much in-phase
  • each rst_root_* starts/stops some derived clock and drive the clock status outputs to pwrmgr
    • pwrmgr waits for all clock status' to be up for a specific state transition, so their arrival time is not important
    • the chip is quiescent while any rst_root is active, since it is coming out of POR

The rstmgr rst_lc_* resets are named rst_* in clkmgr:

  • they control the corresponding clock measurement counters and corresponding CSRs
    • clock measurement is intrinsically tied to a specific clock, and it is not important if they start counting at slightly different times
  • they control the clocking group enables for alert handler
    • these control the outgoing pings, and pings are sent after some number of cycles from when they are enabled and can be considered asynchronous

It seems the small number of cycles between when these resets toggle will not present any issues. I would be comfortable deferring this to a future release, in case some of the rstmgr behavior changes, or there is additional logic driven by these resets.

@andreaskurth andreaskurth added the Triage: deprioritize? temporary label for triage; issue could be deprioritized label May 21, 2024
@andreaskurth andreaskurth removed this from the Earlgrey-PROD.M4 milestone May 24, 2024
@andreaskurth
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triaged to backlog according to the arguments by @matutem and as we're separately verifying CDC and RDC

@andreaskurth andreaskurth added this to the Backlog milestone May 24, 2024
@andreaskurth andreaskurth removed the Triage: deprioritize? temporary label for triage; issue could be deprioritized label May 24, 2024
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Component:DV DV issue: testbench, test case, etc. Earlgrey-PROD Candidate Temporary label to triage issues into Earlgrey-PROD Milestones IP:clkmgr Priority:P2 Priority: medium
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