[clkmgr] D2(S) Signoff

[msfschaffner]

Description

Ensure D2(S) signoff criteria are still maintained (this is not a focus area block).

[matutem]

@msfschaffner here are all changes with a brief description

Commits since Earlgrey-ES tapeout

$ git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/clkmgr/

• 0d14dd6 [docs] Fix repetitions of the definite article
  • no impact
• f95c980 [lint,clkmgr] Clean lint for verible
  • no impact - formatting only
• 7c97490 [clkmgr] Insert hookup buffers on all root clock inputs
  • design impact - insert OCC hook points
• ab4b36f [ipgen,rstmgr] Fix paths to rstmgr in md files
  • no impact - doc only
• c721c51 [rtl, prim] Add 'commit' functionality to prim_count
  • design impact - minimal, since commit_i is set to 1, and cnt_next_o was unused
• 61a237e [util/reggen] reverse order of substruct generation
  • no impact - it only changes the unused clkmgr_reg_plkg.sv in ip/clkmgr
• ce648ca [ipgen.pwrmgr] Change core files to vlnv naming and label as virtual
  • no impact - core file only, change dependency to ip_interfaces:pwrmgr_pkg
• de31bdf [reggen] Remove the devmode input
  • minimal impact - devmode_i was unused
• af22161 [sival,chip_testplans] Handle alert_handler enables tests
  • dv impact minimal - add missing hjson feature label
• 3f88a55 [pwrmgr,ipgen] Generate pwrmgr ip_autogen files with topgen
  • no impact - doc only
• 20c6550 [dv/clkmgr] Fix clkmgr_env.core dependencies
  • no impact - fixes missing dependency in core file
• 897b51e [sival,clkgr] Add features in clkmgr.hjson.tpl
  • dv impact minimal - adds hjson features labels
• 1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
  • no impact - prim_subregs add explicit .Mubi (1'b0) for non-mubi subregs
• 088eee0 [clkmgr,dv] Avoid passing a mubi4_t as a uvm_reg_data_t output arg
  • no impact - fixes xcelium typing warnings
• 59f8142 [doc] Moved badges over to using hosted images: no impact - doc only
• 182f51b [dv/clkmgr] Ignore coverage crosses that are unrealistic
  • dv no impact - only removes obvious coverage holes
• a005c96 [doc] clkmgr registers and interfaces now use CMDGEN
  • no impact - doc only
• 7d0117c [dv/clkmgr] Add test for regwen functionality
  • dv impact minimal - adds a new test
• e8c303f [dv/clkmgr] Fix occasional clkmgr_peri test failure
  • dv impact minimal - fixes occasional test failure
• 0d8b4d4 [dv/clkmgr] Improve handling of clock measure control CSRs
  • dv impact minimal - test code refactoring
• 8ff4837 [dv/clkmgr] Increase wait cycles in clkmgr_lost_calib_ctrl_en_sva_if
  • dv impact minimal - fixes test failures
• bdf5e83 [clkmgr,dv] Fix type in clkmgr_extclk_vseq
  • no impact - lint cleaning
• 7688e71 [reggen] Add initial support for version and cip_id hjson fields
  • no impact - collateral data only
• fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
  • no impact - reverts the change below
• 0ba10b3 [reggen] Add CIP_IDs and bump all major versions
  • no impact - this was reverted
• e47df29 [misc] Use lc_tx_t testing functions at endpoints
  • no impact - code change with no functional impact

Issues closed since the Earlgrey-ES tapeout

• [ip,doc] Fix inaccurate references to reset behavior #20700
• [top_darjeeling] watch dog reset should be mapped to bit 0 #20415
• [chip-test] chip_sw_clkmgr_jitter_cycle_measurements #20230
• [top_earlgrey,tests] Fix clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_test_rom #19620
• [top-level] Clarify uncalibrated IO/SYS/AON clock frequency test #18848
• [clkmgr] Check whether switch to external clock should be disallowed in DEV for production silicon devices #18291
• [ip/clkmgr] clkmgr is missing devmode input. #6104

Currently open issues

• [clkmgr] Make clkmgr DV top-level agnostic #19448
  • This is a multi-top issue
• [dv/clkmgr] Move CSR references from clkmgr_if to clkmgr_csrs_if #18379
  • This is a refactoring request, and is not strictly required
• [dv/clkmgr] Randomize usb_io_clk_en input in clkmgr_peri_vseq #17963
  • This would be good for V3
• [dv/clkmgr] Test different rst_io* and rst_root_io* #17934
  • This has very low value, only causing the derived resets to arrive a few cycles apart, and the net effect is the same.
• [clkmgr] Template exclusions  #16640
  • This could be done to help simplify coverage exclusions, though it is not indispensable
• [dv/rstmgr] Apply different reset kinds where applicable #16148
  • This has a small impact in clkmgr since all CSRs are reset on regular resets. In addition, the base dv_base_vseq apply_reset only resets clk_rst_vif if "kind" == "HARD", which is strange and not helpful.
• [dv] VCS UNR misses simple cases #14304
  • This is an external tool vendor issue, not under our control.
• [top/doc] Autogenerated tables for top-specific IP #12848
  • This is a documentation enhancement.
• [clkmgr, fpga] Enhance clkmgr to allow for different types of clock gates per module #11073
  • This would impact only the fpga, and would be needed if the generated clock trees had problems.
• [ast / clkmgr] Absorb clock dividers directly into ast #11037
  • This is not considered for this release.
• [rtl/mubi] Tighten up mubi CSRs #9273
  • This is not considered for this release.
• [tracking] Use ipgen to produce templated IPs #8440
  • This is in progress, but it should have no impact on the RTL or DV, so it is not indispensable.
• [asserts] Different assert disable condition for clocks #4035
  • This would be good, and should be simple.

Summary

The only design change that has non-trivial impact is
7c97490 [clkmgr] Insert hookup buffers on all root clock inputs: design impact - insert OCC hook points
and then I think this is transparent to our code.

[msfschaffner]

Thanks a lot for the analysis @matutem, this is really helpful.
The OCC hook points should be transparent from a functional perspective, since it just inserts buffers.
No adverse impact from a DV point has been observed, afaik, and Nuvoton/Rivos are already using these in their flows.

I think this looks good and we can sign this block off.
Looks like no further PR is needed since the hjson still shows D2S:

opentitan/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr.hjson

Lines 24 to 32 in 6f25121

	revisions: [
	{
	version: "1.0.0",
	life_stage: "L1",
	design_stage: "D2S",
	verification_stage: "V2S",
	dif_stage: "S2",
	}
	]