[syn] Async FIFO gray pointer timing constraints

[eunchan]

Currently, OpenTitan SDC does not include the Async FIFO timing constraints:

• the max_delay for the gray pointer crossing the clock boundaries.
• Skew within a clock period of other clock domain to ensure only one bit in gray pointer is changed.

[msfschaffner]

How about we add something like this?
@arnonsha can you check in DC whether this would work?

# make sure this is strict, ideally < TCK/2 where TCK is the fastest clock in the system
set MAX_DELAY 5
set SYNC_PATH u_sync_1/gen_*u_impl*/gen_flops[0]*.u_size_only_reg/Q

# for prim_fifo_async.sv
set_max_delay $MAX_DELAY -from [get_pins *] -to [get_pins sync_wptr/$SYNC_PATH]
set_max_delay $MAX_DELAY -from [get_pins *] -to [get_pins sync_rptr/$SYNC_PATH]

# for prim_fifo_async_sram_adapter.sv
set_max_delay $MAX_DELAY -from [get_pins *] -to [get_pins u_sync_wptr_gray/$SYNC_PATH]
set_max_delay $MAX_DELAY -from [get_pins *] -to [get_pins u_sync_rptr_gray/$SYNC_PATH]

[arnonsha]

I'd be happy to try, but in order not to miss anything, could you please write these constraints in full chip level hierarchy ?

thanks

[msfschaffner]

There are many asynchronous FIFO instances in the design (especially in the crossbar). given that the registers have unique names, it would be more economical to try a wildcard for this. maybe we can dump out the list of matches so that we can review them?

[arnonsha]

wildcards is OK, but what I'm trying to say is that the above constraints won't find any cells.
There are no pins in this path: chip_earlgrey_asic/u_sync_wptr_gray/$SYNC_PATH . You need to give the full path from top level.

For example, I found u_sync_wptr_gray in the following path
top_earlgrey.u_spi_device.u_upload.u_cmdfifo.u_sync_wptr_gray

[msfschaffner]

Oh I see. I think we need to use get_pins -hierarchical since there are many instances. I have drafted something here #18581.

[moidx]

Targeting for M2.5.1-RC1. This is trending 2023-05-18.

[johngt]

@moidx / @msfschaffner for updates

[msfschaffner]

#18581 is merged so I am closing this.

Note that SDC tuning for M2.5.2 is tracked separately: #18775