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[spi_device] Remove RDFIFO field
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As the Read FIFO has been increased to max TPM transfer size, 64B,
current DIF, DV test sequence do not use the rdfifo not empty signal nor
rdfifo depth field in `TPM_STATUS`.

In previous commit, the approach to resolve the metastability issue on
RDC was to add 2FF. However, this commit removes the field so that the
data never crosses the reset domain.

Signed-off-by: Eli Kim <[email protected]>
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@eunchan
eunchan committed Oct 27, 2022
1 parent c0995c2 commit f706837
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Showing 5 changed files with 17 additions and 115 deletions.
8 changes: 0 additions & 8 deletions hw/ip/spi_device/data/spi_device.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -1176,14 +1176,6 @@
name: "cmdaddr_notempty"
desc: "If 1, the TPM_CMD_ADDR has a valid data. This status is reported via the interrupt also."
} // f: cmdaddr_notempty
{ bits: "1"
name: "rdfifo_notempty"
desc: "If 1, the TPM_READ_FIFO still has pending data."
} // f: rdfifo_notempty
{ bits: "7+TpmRdFifoPtrW:8"
name: "rdfifo_depth"
desc: "This field represents the current read FIFO depth"
} // f: rdfifo_depth
{ bits: "15+TpmWrFifoPtrW:16"
name: "wrfifo_depth"
desc: "This field represents the current write FIFO depth."
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10 changes: 1 addition & 9 deletions hw/ip/spi_device/rtl/spi_device.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -83,11 +83,8 @@ module spi_device
localparam int unsigned TpmWrFifoDepth = 64; // 64B
localparam int unsigned TpmRdFifoDepth = 16;
localparam int unsigned TpmWrFifoPtrW = $clog2(TpmWrFifoDepth+1);
localparam int unsigned TpmRdFifoPtrW = $clog2(TpmRdFifoDepth+1);
`ASSERT_INIT(TpmWrPtrMatch_A,
TpmWrFifoPtrW == spi_device_reg_pkg::TpmWrFifoPtrW)
`ASSERT_INIT(TpmRdPtrMatch_A,
TpmRdFifoPtrW == spi_device_reg_pkg::TpmRdFifoPtrW)

// Derived parameters

Expand Down Expand Up @@ -365,8 +362,7 @@ module spi_device
logic cfg_tpm_invalid_locality, cfg_tpm_reg_chk_dis;

// TPM_STATUS
logic tpm_status_cmdaddr_notempty, tpm_status_rdfifo_notempty;
logic [TpmRdFifoPtrW-1:0] tpm_status_rdfifo_depth;
logic tpm_status_cmdaddr_notempty;
logic [TpmWrFifoPtrW-1:0] tpm_status_wrfifo_depth;

// TPM ---------------------------------------------------------------
Expand Down Expand Up @@ -1871,8 +1867,6 @@ module spi_device
.sys_rdfifo_wready_o (tpm_rdfifo_wready),

.sys_cmdaddr_notempty_o (tpm_status_cmdaddr_notempty),
.sys_rdfifo_notempty_o (tpm_status_rdfifo_notempty ),
.sys_rdfifo_depth_o (tpm_status_rdfifo_depth ),
.sys_wrfifo_depth_o (tpm_status_wrfifo_depth )
);

Expand All @@ -1895,8 +1889,6 @@ module spi_device
// STATUS:
assign hw2reg.tpm_status = '{
cmdaddr_notempty: '{ de: 1'b 1, d: tpm_status_cmdaddr_notempty },
rdfifo_notempty: '{ de: 1'b 1, d: tpm_status_rdfifo_notempty },
rdfifo_depth: '{ de: 1'b 1, d: tpm_status_rdfifo_depth },
wrfifo_depth: '{ de: 1'b 1, d: tpm_status_wrfifo_depth }
};

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36 changes: 14 additions & 22 deletions hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -653,14 +653,6 @@ package spi_device_reg_pkg;
logic d;
logic de;
} cmdaddr_notempty;
struct packed {
logic d;
logic de;
} rdfifo_notempty;
struct packed {
logic [4:0] d;
logic de;
} rdfifo_depth;
struct packed {
logic [6:0] d;
logic de;
Expand Down Expand Up @@ -727,20 +719,20 @@ package spi_device_reg_pkg;

// HW -> register type
typedef struct packed {
spi_device_hw2reg_intr_state_reg_t intr_state; // [290:267]
spi_device_hw2reg_cfg_reg_t cfg; // [266:265]
spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level; // [264:249]
spi_device_hw2reg_status_reg_t status; // [248:242]
spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr; // [241:225]
spi_device_hw2reg_txf_ptr_reg_t txf_ptr; // [224:208]
spi_device_hw2reg_last_read_addr_reg_t last_read_addr; // [207:176]
spi_device_hw2reg_flash_status_reg_t flash_status; // [175:152]
spi_device_hw2reg_upload_status_reg_t upload_status; // [151:136]
spi_device_hw2reg_upload_status2_reg_t upload_status2; // [135:117]
spi_device_hw2reg_upload_cmdfifo_reg_t upload_cmdfifo; // [116:109]
spi_device_hw2reg_upload_addrfifo_reg_t upload_addrfifo; // [108:77]
spi_device_hw2reg_tpm_cap_reg_t tpm_cap; // [76:58]
spi_device_hw2reg_tpm_status_reg_t tpm_status; // [57:40]
spi_device_hw2reg_intr_state_reg_t intr_state; // [282:259]
spi_device_hw2reg_cfg_reg_t cfg; // [258:257]
spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level; // [256:241]
spi_device_hw2reg_status_reg_t status; // [240:234]
spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr; // [233:217]
spi_device_hw2reg_txf_ptr_reg_t txf_ptr; // [216:200]
spi_device_hw2reg_last_read_addr_reg_t last_read_addr; // [199:168]
spi_device_hw2reg_flash_status_reg_t flash_status; // [167:144]
spi_device_hw2reg_upload_status_reg_t upload_status; // [143:128]
spi_device_hw2reg_upload_status2_reg_t upload_status2; // [127:109]
spi_device_hw2reg_upload_cmdfifo_reg_t upload_cmdfifo; // [108:101]
spi_device_hw2reg_upload_addrfifo_reg_t upload_addrfifo; // [100:69]
spi_device_hw2reg_tpm_cap_reg_t tpm_cap; // [68:50]
spi_device_hw2reg_tpm_status_reg_t tpm_status; // [49:40]
spi_device_hw2reg_tpm_cmd_addr_reg_t tpm_cmd_addr; // [39:8]
spi_device_hw2reg_tpm_write_fifo_reg_t tpm_write_fifo; // [7:0]
} spi_device_hw2reg_t;
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56 changes: 0 additions & 56 deletions hw/ip/spi_device/rtl/spi_device_reg_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1510,8 +1510,6 @@ module spi_device_reg_top (
logic tpm_cfg_invalid_locality_qs;
logic tpm_cfg_invalid_locality_wd;
logic tpm_status_cmdaddr_notempty_qs;
logic tpm_status_rdfifo_notempty_qs;
logic [4:0] tpm_status_rdfifo_depth_qs;
logic [6:0] tpm_status_wrfifo_depth_qs;
logic tpm_access_0_we;
logic [7:0] tpm_access_0_access_0_qs;
Expand Down Expand Up @@ -18469,58 +18467,6 @@ module spi_device_reg_top (
.qs (tpm_status_cmdaddr_notempty_qs)
);

// F[rdfifo_notempty]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_tpm_status_rdfifo_notempty (
.clk_i (clk_i),
.rst_ni (rst_ni),

// from register interface
.we (1'b0),
.wd ('0),

// from internal hardware
.de (hw2reg.tpm_status.rdfifo_notempty.de),
.d (hw2reg.tpm_status.rdfifo_notempty.d),

// to internal hardware
.qe (),
.q (),
.ds (),

// to register interface (read)
.qs (tpm_status_rdfifo_notempty_qs)
);

// F[rdfifo_depth]: 12:8
prim_subreg #(
.DW (5),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (5'h0)
) u_tpm_status_rdfifo_depth (
.clk_i (clk_i),
.rst_ni (rst_ni),

// from register interface
.we (1'b0),
.wd ('0),

// from internal hardware
.de (hw2reg.tpm_status.rdfifo_depth.de),
.d (hw2reg.tpm_status.rdfifo_depth.d),

// to internal hardware
.qe (),
.q (),
.ds (),

// to register interface (read)
.qs (tpm_status_rdfifo_depth_qs)
);

// F[wrfifo_depth]: 22:16
prim_subreg #(
.DW (7),
Expand Down Expand Up @@ -21453,8 +21399,6 @@ module spi_device_reg_top (

addr_hit[66]: begin
reg_rdata_next[0] = tpm_status_cmdaddr_notempty_qs;
reg_rdata_next[1] = tpm_status_rdfifo_notempty_qs;
reg_rdata_next[12:8] = tpm_status_rdfifo_depth_qs;
reg_rdata_next[22:16] = tpm_status_wrfifo_depth_qs;
end

Expand Down
22 changes: 2 additions & 20 deletions hw/ip/spi_device/rtl/spi_tpm.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -134,8 +134,6 @@ module spi_tpm

// TPM_STATUS
output logic sys_cmdaddr_notempty_o,
output logic sys_rdfifo_notempty_o,
output logic [RdFifoPtrW-1:0] sys_rdfifo_depth_o,
output logic [WrFifoPtrW-1:0] sys_wrfifo_depth_o
);

Expand Down Expand Up @@ -371,7 +369,7 @@ module spi_tpm
// Read FIFO uses inverted SCK (clk_out_i)
logic isck_rdfifo_rvalid, isck_rdfifo_rready;
logic [RdFifoWidth-1:0] isck_rdfifo_rdata;
logic [RdFifoPtrW-1:0] sys_rdfifo_wdepth, isck_rdfifo_rdepth;
logic [RdFifoPtrW-1:0] isck_rdfifo_rdepth;

logic [RdFifoOffsetW-1:0] isck_rdfifo_idx;
logic isck_rd_byte_sent;
Expand Down Expand Up @@ -1207,7 +1205,7 @@ module spi_tpm
.wvalid_i (sys_rdfifo_wvalid_i),
.wready_o (sys_rdfifo_wready_o),
.wdata_i (sys_rdfifo_wdata_i),
.wdepth_o (sys_rdfifo_wdepth),
.wdepth_o (),

.clk_rd_i (clk_out_i),
.rst_rd_ni (rst_n),
Expand All @@ -1218,22 +1216,6 @@ module spi_tpm

);

// When CS# is de-asserted, there's chance the sys_rdfifo becomes metastable
// as RDFIFO reset is CS# (after async assert, sync de-assert rst sync logic)
// One solution is to change the rst sync to sync assert sync de-assert.
// However, it creates extra latency to the CS# inactive time. In this
// module, the logic simply latches the depth signal to remove the
// metastable state.
prim_flop_2sync #(
.Width (RdFifoPtrW)
) u_rdfifo_depth_sync (
.clk_i (sys_clk_i),
.rst_ni (sys_rst_ni),
.d_i (sys_rdfifo_wdepth),
.q_o (sys_rdfifo_depth_o)
);
assign sys_rdfifo_notempty_o = |sys_rdfifo_depth_o;

// Logic Not Used
logic unused_logic;
assign unused_logic = ^{ sck_cmdaddr_wready,
Expand Down

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