[csrng/rtl] Change and assign cmd_sts signal

This commit changes the sw_cmd_sts and hw_cmd_sts signals to multiple bits. 0 represents a successful acknowledgement, whereas any value other than 0 represents an error status. The sts signal is now also able to anounce to the EDN that the CSRNG main SM is hanging due to an invalid acmd. This commit also aligns the EDN rtl with the new sts response. Furthermore a new csrng interface pkg is created to avoid circular dependencies. This commit also aligns the EDN and CSRNG DV, documentation and SW with the new STS signal. Signed-off-by: Hakim Filali <[email protected]>
lowRISC · Mar 25, 2024 · d7b809d · d7b809d
1 parent b36afc1
commit d7b809d
Show file tree

Hide file tree

Showing 32 changed files with 503 additions and 437 deletions.
diff --git a/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv b/hw/dv/sv/csrng_agent/csrng_agent_cfg.sv
@@ -15,13 +15,13 @@ class csrng_agent_cfg extends dv_base_agent_cfg;
 
   `uvm_object_new
 
-  uint   min_cmd_ack_dly, max_cmd_ack_dly,
-         min_genbits_dly, max_genbits_dly,
-         min_genbits_rdy_dly, max_genbits_rdy_dly,
-         min_cmd_rdy_dly, max_cmd_rdy_dly,
-         reseed_cnt, generate_cnt, generate_between_reseeds_cnt;
-  bit    cmd_zero_delays;
-  bit    under_reset;
-  bit    rsp_sts_err;
+  uint              min_cmd_ack_dly, max_cmd_ack_dly,
+                    min_genbits_dly, max_genbits_dly,
+                    min_genbits_rdy_dly, max_genbits_rdy_dly,
+                    min_cmd_rdy_dly, max_cmd_rdy_dly,
+                    reseed_cnt, generate_cnt, generate_between_reseeds_cnt;
+  bit               cmd_zero_delays;
+  bit               under_reset;
+  csrng_cmd_sts_e   rsp_sts_err;
 
 endclass
diff --git a/hw/dv/sv/csrng_agent/csrng_device_driver.sv b/hw/dv/sv/csrng_agent/csrng_device_driver.sv
@@ -16,7 +16,7 @@ class csrng_device_driver extends csrng_driver;
 
   virtual task reset_signals();
     cfg.vif.cmd_rsp_int.csrng_rsp_ack <= 1'b0;
-    cfg.vif.cmd_rsp_int.csrng_rsp_sts <= 1'b0;
+    cfg.vif.cmd_rsp_int.csrng_rsp_sts <= CMD_STS_SUCCESS;
   endtask
 
   // drive trans received from sequencer
@@ -35,7 +35,7 @@ class csrng_device_driver extends csrng_driver;
           cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= cfg.rsp_sts_err;
           @(cfg.vif.device_cb);
           cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_ack <= 1'b0;
-          cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= 1'b0;,
+          cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= CMD_STS_SUCCESS;,
           wait (cfg.under_reset == 1);)
 
       // Write ack bit again in case the race condition with `reset_signals`.

diff --git a/hw/dv/sv/csrng_agent/csrng_if.sv b/hw/dv/sv/csrng_agent/csrng_if.sv
@@ -30,7 +30,8 @@ interface csrng_if (input clk, input rst_n);
   assign cmd_push_if.valid     = (if_mode == dv_utils_pkg::Device) ? cmd_req.csrng_req_valid : 'z;
   assign cmd_push_if.h_data    = (if_mode == dv_utils_pkg::Device) ? cmd_req.csrng_req_bus : 'z;
   assign cmd_rsp.csrng_rsp_ack = (if_mode == dv_utils_pkg::Device) ? cmd_rsp_int.csrng_rsp_ack : 'z;
-  assign cmd_rsp.csrng_rsp_sts = (if_mode == dv_utils_pkg::Device) ? cmd_rsp_int.csrng_rsp_sts : 'z;
+  assign cmd_rsp.csrng_rsp_sts = (if_mode == dv_utils_pkg::Device) ?
+                                 cmd_rsp_int.csrng_rsp_sts : CMD_STS_UNDRIVEN;
 
   assign genbits_push_if.ready = (if_mode == dv_utils_pkg::Device) ? cmd_req.genbits_ready : 'z;
   assign cmd_rsp.genbits_valid = (if_mode == dv_utils_pkg::Device) ? genbits_push_if.valid : 'z;

diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson
@@ -325,20 +325,45 @@
       tags: [// Internal HW can modify status register
                  "excl:CsrNonInitTests:CsrExclCheck"]
       fields: [
-        { bits: "0",
+        { bits: "1",
           name: "CMD_RDY",
-          desc: '''This bit indicates when the command interface is ready to accept commands.
+          desc: '''
+                This bit indicates when the command interface is ready to accept commands.
+                Before starting to write a new command to !!SW_CMD_REQ, this field needs to be polled.
+                0b0: CSRNG is not ready to accept commands or the last command hasn't been acked yet.
+                0b1: CSRNG is ready to accept the next command.
                 '''
-          resval: "1"
+          resval: "0"
         }
-        { bits: "1",
+        { bits: "2",
+          name: "CMD_ACK",
+          desc: '''
+                This one bit field indicates when a SW command has been acknowledged by the CSRNG.
+                It is set to low each time a new command is written to !!CMD_REQ.
+                The field is set to high once a SW command request has been acknowledged by the CSRNG.
+                0b0: The last SW command has not been acknowledged yet.
+                0b1: The last SW command has been acknowledged.
+                '''
+          resval: "0"
+        }
+        { bits: "4:3",
           name: "CMD_STS",
           desc: '''
-                This one bit field is the status code returned with the application command ack.
+                This field represents the status code returned with the application command ack.
                 It is updated each time a command ack is asserted on the internal application
                 interface for software use.
-                0b0: Request completed successfully
-                0b1: Request completed with an error
+                To check whether a command was succesful, wait for !!INTR_STATE.CS_CMD_REQ_DONE or
+                !!SW_CMD_STS.CMD_ACK to be high and then check the value of this field.
+                0b00: Request completed successfully.
+                0b01: Request completed with an invalid application command error.
+                      This error indicates that the issued application command doesn't represent a valid operation.
+                      If this error appears, the main state machine will hang and the entropy complex has to be restarted.
+                0b10: Request completed with an invalid state parameter error.
+                      This error indicates that the state wasn't zeroized properly after an uninstantiate command.
+                      In this case the entropy complex should be restarted to properly zeroize the state.
+                0b11: Request completed with an invalid counter drbg generation command error.
+                      This error indicates that CSRNG entropy was generated for a command that is not a generate command.
+                      In this case the entropy should not be considered as valid.
                 '''
           resval: "0"
         }

diff --git a/hw/ip/csrng/doc/registers.md b/hw/ip/csrng/doc/registers.md
@@ -157,30 +157,51 @@ Command request register
 ## SW_CMD_STS
 Application interface command status register
 - Offset: `0x1c`
-- Reset default: `0x1`
-- Reset mask: `0x3`
+- Reset default: `0x0`
+- Reset mask: `0x1e`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+{"reg": [{"bits": 1}, {"name": "CMD_RDY", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_ACK", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_STS", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                            |
 |:------:|:------:|:-------:|:--------------------------------|
-|  31:2  |        |         | Reserved                        |
-|   1    |   ro   |   0x0   | [CMD_STS](#sw_cmd_sts--cmd_sts) |
-|   0    |   ro   |   0x1   | [CMD_RDY](#sw_cmd_sts--cmd_rdy) |
+|  31:5  |        |         | Reserved                        |
+|  4:3   |   ro   |   0x0   | [CMD_STS](#sw_cmd_sts--cmd_sts) |
+|   2    |   ro   |   0x0   | [CMD_ACK](#sw_cmd_sts--cmd_ack) |
+|   1    |   ro   |   0x0   | [CMD_RDY](#sw_cmd_sts--cmd_rdy) |
 
 ### SW_CMD_STS . CMD_STS
-This one bit field is the status code returned with the application command ack.
+This field represents the status code returned with the application command ack.
 It is updated each time a command ack is asserted on the internal application
 interface for software use.
-0b0: Request completed successfully
-0b1: Request completed with an error
+To check whether a command was succesful, wait for [`INTR_STATE.CS_CMD_REQ_DONE`](#intr_state) or
+[`SW_CMD_STS.CMD_ACK`](#sw_cmd_sts) to be high and then check the value of this field.
+0b00: Request completed successfully.
+0b01: Request completed with an invalid application command error.
+      This error indicates that the issued application command doesn't represent a valid operation.
+      If this error appears, the main state machine will hang and the entropy complex has to be restarted.
+0b10: Request completed with an invalid state parameter error.
+      This error indicates that the state wasn't zeroized properly after an uninstantiate command.
+      In this case the entropy complex should be restarted to properly zeroize the state.
+0b11: Request completed with an invalid counter drbg generation command error.
+      This error indicates that CSRNG entropy was generated for a command that is not a generate command.
+      In this case the entropy should not be considered as valid.
+
+### SW_CMD_STS . CMD_ACK
+This one bit field indicates when a SW command has been acknowledged by the CSRNG.
+It is set to low each time a new command is written to [`CMD_REQ.`](#cmd_req)
+The field is set to high once a SW command request has been acknowledged by the CSRNG.
+0b0: The last SW command has not been acknowledged yet.
+0b1: The last SW command has been acknowledged.
 
 ### SW_CMD_STS . CMD_RDY
 This bit indicates when the command interface is ready to accept commands.
+Before starting to write a new command to [`SW_CMD_REQ`](#sw_cmd_req), this field needs to be polled.
+0b0: CSRNG is not ready to accept commands or the last command hasn't been acked yet.
+0b1: CSRNG is ready to accept the next command.
 
 ## GENBITS_VLD
 Generate bits returned valid register

diff --git a/hw/ip/csrng/rtl/csrng_cmd_stage.sv b/hw/ip/csrng/rtl/csrng_cmd_stage.sv
@@ -27,10 +27,10 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   output logic [CmdFifoWidth-1:0]    cmd_arb_bus_o,
   // Ack from core.
   input logic                        cmd_ack_i,
-  input logic                        cmd_ack_sts_i,
+  input csrng_cmd_sts_e              cmd_ack_sts_i,
   // Ack to app i/f.
   output logic                       cmd_stage_ack_o,
-  output logic                       cmd_stage_ack_sts_o,
+  output csrng_cmd_sts_e             cmd_stage_ack_sts_o,
   // Genbits from core.
   input logic                        genbits_vld_i,
   input logic [127:0]                genbits_bus_i,
@@ -85,7 +85,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
 
   // Flops.
   logic                    cmd_ack_q, cmd_ack_d;
-  logic                    cmd_ack_sts_q, cmd_ack_sts_d;
+  csrng_cmd_sts_e          cmd_ack_sts_q, cmd_ack_sts_d;
   logic [3:0]              cmd_len_q, cmd_len_d;
   logic                    cmd_gen_flag_q, cmd_gen_flag_d;
   logic [11:0]             cmd_gen_cmd_q, cmd_gen_cmd_d;
@@ -96,7 +96,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   always_ff @(posedge clk_i or negedge rst_ni)
     if (!rst_ni) begin
       cmd_ack_q       <= '0;
-      cmd_ack_sts_q   <= '0;
+      cmd_ack_sts_q   <= CMD_STS_SUCCESS;
       cmd_len_q       <= '0;
       cmd_gen_flag_q  <= '0;
       cmd_gen_cmd_q   <= '0;
@@ -413,7 +413,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   assign cmd_stage_ack_o = cmd_ack_q;
 
   assign cmd_ack_sts_d =
-         (!cs_enable_i) ? '0 :
+         (!cs_enable_i) ? CMD_STS_SUCCESS :
          cmd_final_ack ? cmd_ack_sts_i :
          cmd_ack_sts_q;