[adc_ctrl] Updates to LP -> NP transition

Signed-off-by: Michael Schaffner <[email protected]>
lowRISC · Mar 5, 2024 · b9a1454 · b9a1454
1 parent 0632d2f
commit b9a1454
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Showing 11 changed files with 508 additions and 172 deletions.
diff --git a/hw/ip/adc_ctrl/data/adc_ctrl.hjson b/hw/ip/adc_ctrl/data/adc_ctrl.hjson
@@ -306,8 +306,29 @@
       resval: "0",
       fields: [
         { bits: "NumAdcFilter-1:0",
-          name: "EN",
-          desc: "0: filter match wil not generate wakeupe; 1: filter match will generate wakeup",
+          name: "MATCH_EN",
+          desc: '''
+          Filter wakeup source.
+
+          0: filter match will not generate wakeup;
+          1: filter match will generate wakeup
+          '''
+        }
+        {
+          bits: "NumAdcFilter:NumAdcFilter",
+          name: "TRANS_EN",
+          desc: '''
+          Wakeup due to FSM transition from low power sampling
+          mode to normal sampling mode.
+
+          Note that this wakeup source is primarily intended for debug purposes.
+          If enabled all the time, this can lead to many wakeups due to false
+          positives that are ruled out automatically by adc_ctrl after
+          transitioning from LP -> NP.
+
+          0: transition match will not generate wakeup;
+          1: transition match will generate wakeup
+          '''
         }
       ]
     }
@@ -324,9 +345,13 @@
       resval: "0",
       fields: [
         { bits: "7:0",
-          name: "COND",
+          name: "MATCH",
           desc: "0: filter condition is not met; 1: filter condition is met",
         }
+        { bits: "NumAdcFilter:NumAdcFilter",
+          name: "TRANS",
+          desc: "0: transition did not occur; 1: transition occurred",
+        }
       ]
     }
 
@@ -343,10 +368,36 @@
       hwaccess: "hro",
       resval: "0",
       fields: [
-        { bits: "8:0",
-          name: "EN",
-          desc: "0: interrupt source is not enabled; 1: interrupt source is enabled",
+        { bits: "NumAdcFilter-1:0",
+          name: "MATCH_EN",
+          desc: '''
+          Filter interrupt source.
+
+          0: interrupt source is not enabled; 1: interrupt source is enabled
+          '''
+        }
+        {
+          bits: "NumAdcFilter:NumAdcFilter",
+          name: "TRANS_EN",
+          desc: '''
+          Interrupt due to FSM transition from low power sampling
+          mode to normal sampling mode. This is mainly intended for debug.
+
+          Note that this interrupt is primarily intended for debug purposes.
+
+          0: interrupt source is not enabled; 1: interrupt source is enabled
+          '''
         }
+        {
+          bits: "NumAdcFilter+1:NumAdcFilter+1",
+          name: "ONESHOT_EN",
+          desc: '''
+          Interrupt due to oneshot sampling.
+
+          0: interrupt source is not enabled; 1: interrupt source is enabled
+          '''
+        }
+
       ]
     }
 
@@ -360,11 +411,15 @@
               "excl:CsrNonInitTests:CsrExclCheck"],
       fields: [
         { bits: "NumAdcFilter-1:0",
-          name: "filter_match",
+          name: "MATCH",
           desc: "0: filter condition is not met; 1: filter condition is met",
         }
         { bits: "NumAdcFilter:NumAdcFilter",
-          name: "oneshot",
+          name: "TRANS",
+          desc: "0: transition did not occur; 1: transition occurred",
+        }
+        { bits: "NumAdcFilter+1:NumAdcFilter+1",
+          name: "ONESHOT",
           desc: "0: oneshot sample is not done ; 1: oneshot sample is done",
         }
       ]

diff --git a/hw/ip/adc_ctrl/doc/registers.md b/hw/ip/adc_ctrl/doc/registers.md
@@ -304,37 +304,57 @@ ADC value sampled on channel
 Enable filter matches as wakeups
 - Offset: `0x6c`
 - Reset default: `0x0`
-- Reset mask: `0xff`
+- Reset mask: `0x1ff`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "EN", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+{"reg": [{"name": "MATCH_EN", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TRANS_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
 ```
 
-|  Bits  |  Type  |  Reset  | Name   | Description                                                                    |
-|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------|
-|  31:8  |        |         |        | Reserved                                                                       |
-|  7:0   |   rw   |   0x0   | EN     | 0: filter match wil not generate wakeupe; 1: filter match will generate wakeup |
+|  Bits  |  Type  |  Reset  | Name                                  |
+|:------:|:------:|:-------:|:--------------------------------------|
+|  31:9  |        |         | Reserved                              |
+|   8    |   rw   |   0x0   | [TRANS_EN](#adc_wakeup_ctl--trans_en) |
+|  7:0   |   rw   |   0x0   | [MATCH_EN](#adc_wakeup_ctl--match_en) |
+
+### adc_wakeup_ctl . TRANS_EN
+Wakeup due to FSM transition from low power sampling
+mode to normal sampling mode.
+
+Note that this wakeup source is primarily intended for debug purposes.
+If enabled all the time, this can lead to many wakeups due to false
+positives that are ruled out automatically by adc_ctrl after
+transitioning from LP -> NP.
+
+0: transition match will not generate wakeup;
+1: transition match will generate wakeup
+
+### adc_wakeup_ctl . MATCH_EN
+Filter wakeup source.
+
+0: filter match will not generate wakeup;
+1: filter match will generate wakeup
 
 ## filter_status
 Adc filter match status
 
 Indicates whether a particular filter has matched on all channels.
 - Offset: `0x70`
 - Reset default: `0x0`
-- Reset mask: `0xff`
+- Reset mask: `0x1ff`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "COND", "bits": 8, "attr": ["rw1c"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+{"reg": [{"name": "MATCH", "bits": 8, "attr": ["rw1c"], "rotate": 0}, {"name": "TRANS", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name   | Description                                                |
 |:------:|:------:|:-------:|:-------|:-----------------------------------------------------------|
-|  31:8  |        |         |        | Reserved                                                   |
-|  7:0   |  rw1c  |   0x0   | COND   | 0: filter condition is not met; 1: filter condition is met |
+|  31:9  |        |         |        | Reserved                                                   |
+|   8    |  rw1c  |   0x0   | TRANS  | 0: transition did not occur; 1: transition occurred        |
+|  7:0   |  rw1c  |   0x0   | MATCH  | 0: filter condition is not met; 1: filter condition is met |
 
 ## adc_intr_ctl
 Interrupt enable controls.
@@ -345,36 +365,57 @@ which internal sources are actually registered.
 This register uses the same bit enumeration as [`ADC_INTR_STATUS`](#adc_intr_status)
 - Offset: `0x74`
 - Reset default: `0x0`
-- Reset mask: `0x1ff`
+- Reset mask: `0x3ff`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "EN", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+{"reg": [{"name": "MATCH_EN", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TRANS_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ONESHOT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}
 ```
 
-|  Bits  |  Type  |  Reset  | Name   | Description                                                        |
-|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------|
-|  31:9  |        |         |        | Reserved                                                           |
-|  8:0   |   rw   |   0x0   | EN     | 0: interrupt source is not enabled; 1: interrupt source is enabled |
+|  Bits  |  Type  |  Reset  | Name                                    |
+|:------:|:------:|:-------:|:----------------------------------------|
+| 31:10  |        |         | Reserved                                |
+|   9    |   rw   |   0x0   | [ONESHOT_EN](#adc_intr_ctl--oneshot_en) |
+|   8    |   rw   |   0x0   | [TRANS_EN](#adc_intr_ctl--trans_en)     |
+|  7:0   |   rw   |   0x0   | [MATCH_EN](#adc_intr_ctl--match_en)     |
+
+### adc_intr_ctl . ONESHOT_EN
+Interrupt due to oneshot sampling.
+
+0: interrupt source is not enabled; 1: interrupt source is enabled
+
+### adc_intr_ctl . TRANS_EN
+Interrupt due to FSM transition from low power sampling
+mode to normal sampling mode. This is mainly intended for debug.
+
+Note that this interrupt is primarily intended for debug purposes.
+
+0: interrupt source is not enabled; 1: interrupt source is enabled
+
+### adc_intr_ctl . MATCH_EN
+Filter interrupt source.
+
+0: interrupt source is not enabled; 1: interrupt source is enabled
 
 ## adc_intr_status
 Debug cable internal status
 - Offset: `0x78`
 - Reset default: `0x0`
-- Reset mask: `0x1ff`
+- Reset mask: `0x3ff`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "filter_match", "bits": 8, "attr": ["rw1c"], "rotate": 0}, {"name": "oneshot", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
+{"reg": [{"name": "MATCH", "bits": 8, "attr": ["rw1c"], "rotate": 0}, {"name": "TRANS", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ONESHOT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
 ```
 
-|  Bits  |  Type  |  Reset  | Name         | Description                                                |
-|:------:|:------:|:-------:|:-------------|:-----------------------------------------------------------|
-|  31:9  |        |         |              | Reserved                                                   |
-|   8    |  rw1c  |   0x0   | oneshot      | 0: oneshot sample is not done ; 1: oneshot sample is done  |
-|  7:0   |  rw1c  |   0x0   | filter_match | 0: filter condition is not met; 1: filter condition is met |
+|  Bits  |  Type  |  Reset  | Name    | Description                                                |
+|:------:|:------:|:-------:|:--------|:-----------------------------------------------------------|
+| 31:10  |        |         |         | Reserved                                                   |
+|   9    |  rw1c  |   0x0   | ONESHOT | 0: oneshot sample is not done ; 1: oneshot sample is done  |
+|   8    |  rw1c  |   0x0   | TRANS   | 0: transition did not occur; 1: transition occurred        |
+|  7:0   |  rw1c  |   0x0   | MATCH   | 0: filter condition is not met; 1: filter condition is met |
 
 ## adc_fsm_state
 State of the internal state machine

diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl.sv
@@ -93,9 +93,12 @@ module adc_ctrl
     .intr_o(intr_match_done_o),
     .adc_i(adc_i),
     .adc_o(adc_o),
-    .fsm_state_o(hw2reg.adc_fsm_state.d)
+    .aon_fsm_state_o(hw2reg.adc_fsm_state.d)
   );
 
+
+
+
   // All outputs should be known value after reset
   `ASSERT_KNOWN(IntrKnown, intr_match_done_o)
   `ASSERT_KNOWN(WakeKnown, wkup_req_o)

diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv
@@ -28,14 +28,15 @@ module adc_ctrl_core import adc_ctrl_reg_pkg::* ; (
   output ast_pkg::adc_ast_req_t adc_o,
 
   // FSM state output for debug purposes.
-  output fsm_state_e fsm_state_o
+  output adc_ctrl_pkg::fsm_state_e aon_fsm_state_o
 );
 
   logic chn0_val_we, chn1_val_we;//write enable for the latest ADC sample
   logic [9:0] chn0_val, chn1_val;
 
   logic [NumAdcFilter-1:0] chn0_match, chn1_match, match;
   logic [NumAdcFilter-1:0] match_pulse;
+  logic aon_fsm_trans;
 
   //write enable for the ADC sample when the interrupt is triggered
   logic adc_ctrl_done, oneshot_done;
@@ -133,13 +134,18 @@ module adc_ctrl_core import adc_ctrl_reg_pkg::* ; (
   end
 
   // adc filter status
-  assign aon_filter_status_o.d  = match_pulse | reg2hw_i.filter_status.q;
-  assign aon_filter_status_o.de = |match_pulse;
+  assign aon_filter_status_o.filter_match.d  = match_pulse | reg2hw_i.filter_status.filter_match.q;
+  assign aon_filter_status_o.filter_match.de = |match_pulse;
+  // transition status
+  assign aon_filter_status_o.trans.d  = aon_fsm_trans | reg2hw_i.filter_status.trans.q;
+  assign aon_filter_status_o.trans.de = aon_fsm_trans;
 
   // generate wakeup to external power manager if filter status
   // and wakeup enable are set.
-  assign wkup_req_o = |(reg2hw_i.filter_status.q &
-                      reg2hw_i.adc_wakeup_ctl.q);
+  assign wkup_req_o = |(reg2hw_i.filter_status.filter_match.q &
+                        reg2hw_i.adc_wakeup_ctl.filter_match.q) ||
+                       (reg2hw_i.filter_status.trans.q &
+                        reg2hw_i.adc_wakeup_ctl.trans.q);
 
   //instantiate the main state machine
   adc_ctrl_fsm u_adc_ctrl_fsm (
@@ -166,7 +172,8 @@ module adc_ctrl_core import adc_ctrl_reg_pkg::* ; (
     .chn1_val_o(chn1_val),
     .adc_ctrl_done_o(adc_ctrl_done),
     .oneshot_done_o(oneshot_done),
-    .fsm_state_o
+    .aon_fsm_state_o,
+    .aon_fsm_trans_o(aon_fsm_trans)
   );
 
   // synchronzie from clk_aon into cfg domain
@@ -182,13 +189,18 @@ module adc_ctrl_core import adc_ctrl_reg_pkg::* ; (
 
   //Instantiate the interrupt module
   adc_ctrl_intr u_adc_ctrl_intr (
+    .clk_i,
+    .rst_ni,
     .clk_aon_i,
     .rst_aon_ni,
     .aon_filter_match_i(match_pulse),
-    .clk_i,
-    .rst_ni,
-    .cfg_intr_en_i(reg2hw_i.adc_intr_ctl.q),
+    .aon_fsm_trans_i(aon_fsm_trans),
     .cfg_oneshot_done_i(cfg_oneshot_done),
+    .cfg_intr_en_i(reg2hw_i.adc_intr_ctl.en.q),
+    .cfg_wkup_en_i(reg2hw_i.adc_wakeup_ctl.en.q),
+    .cfg_intr_trans_en_i(reg2hw_i.adc_intr_ctl.trans_en.q),
+    .cfg_wkup_trans_en_i(reg2hw_i.adc_wakeup_ctl.trans_en.q),
+    .cfg_oneshot_done_en_i(reg2hw_i.adc_intr_ctl.oneshot_en.q),
     .intr_state_i(reg2hw_i.intr_state),
     .intr_enable_i(reg2hw_i.intr_enable),
     .intr_test_i(reg2hw_i.intr_test),

diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl_fsm.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl_fsm.sv
@@ -29,7 +29,8 @@ module adc_ctrl_fsm
   output logic [9:0] chn1_val_o,
   output logic       adc_ctrl_done_o,
   output logic       oneshot_done_o,
-  output fsm_state_e fsm_state_o // FSM state output for debug purposes
+  output fsm_state_e aon_fsm_state_o, // FSM state output for debug purposes
+  output logic       aon_fsm_trans_o // FSM lp -> np transition indication pulse
 );
 
   logic trigger_q;
@@ -54,7 +55,7 @@ module adc_ctrl_fsm
 
 
   fsm_state_e fsm_state_q, fsm_state_d;
-  assign fsm_state_o = fsm_state_q;
+  assign aon_fsm_state_o = fsm_state_q;
 
   always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
     if (!rst_aon_ni) begin
@@ -185,7 +186,6 @@ module adc_ctrl_fsm
   assign lp_sample_cnt_thresh = cfg_lp_sample_cnt_i - 1'b1;
   assign np_sample_cnt_thresh = cfg_np_sample_cnt_i - 1'b1;
 
-
   always_comb begin: adc_fsm
     fsm_state_d = fsm_state_q;
     //outputs
@@ -202,6 +202,7 @@ module adc_ctrl_fsm
     adc_ctrl_done_o = 1'b0;
     oneshot_done_o = 1'b0;
     ld_match = 1'b0;
+    aon_fsm_trans_o = 1'b0;
 
     unique case (fsm_state_q)
       PWRDN: begin
@@ -289,6 +290,7 @@ module adc_ctrl_fsm
           end else if (lp_sample_cnt_q == lp_sample_cnt_thresh) begin
             fsm_state_d = NP_0;
             lp_sample_cnt_clr = 1'b1;
+            aon_fsm_trans_o = 1'b1;
           end
         end
       end