[entropy_src/doc] Fix documentation of security countermeausures

Signed-off-by: Pirmin Vogel <[email protected]>

hw/ip/entropy_src/data/entropy_src.hjson

@@ -1710,21 +1710,21 @@
         { bits: "28",
           name: "FIFO_WRITE_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
+                This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
                 This bit will stay set until the next reset.
                 '''
         }
         { bits: "29",
           name: "FIFO_READ_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
+                This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
                 This bit will stay set until the next reset.
                 '''
         }
         { bits: "30",
           name: "FIFO_STATE_ERR",
           desc: '''
-                This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
+                This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
                 This bit will stay set until the next reset.
                 '''
         }

hw/ip/entropy_src/doc/registers.md

@@ -1510,15 +1510,15 @@ Hardware detection of error conditions status register
 |   0    |   ro   |   0x0   | [SFIFO_ESRNG_ERR](#err_code--sfifo_esrng_err)           |
 
 ### ERR_CODE . FIFO_STATE_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
+This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any FIFO where either both the empty and full status bits are set or in case of error conditions inside the hardened counters.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . FIFO_READ_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
+This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any empty FIFO that has received a read pulse.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . FIFO_WRITE_ERR
-This bit will be set to one when any of the source bits (bits 0 through 1 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
+This bit will be set to one when any of the source bits (bits 0 through 3 of this register) are asserted as a result of an error pulse generated from any full FIFO that has been received a write pulse.
 This bit will stay set until the next reset.
 
 ### ERR_CODE . SHA3_RST_STORAGE_ERR

hw/ip/entropy_src/doc/theory_of_operation.md

@@ -121,7 +121,7 @@ See the [programmer's guide section](programmers_guide.md/#entropy-source-module
 
 ### Security
 
-All module assets and countermeasures performed by hardware are listed in the hjson countermeasures section.
+All module assets and countermeasures performed by hardware are listed in the [countermeasures section](interfaces.md/#security-countermeasures).
 Labels for each instance of asset and countermeasure are located throughout the RTL source code.
 
 A configuration and control register locking function is performed by the [`REGWEN`](registers.md#regwen) register.
@@ -136,7 +136,6 @@ Bus integrity checking is performed for the final seed delivery to CSRNG.
 This is done to make sure repeated values are not occurring.
 Only 64 bits (out of 384 bits) are checked, since this is statistically significant, and more checking would cost more silicon.
 
-
 ### Main State Machine Diagram
 The following diagram shows how the main state machine state is constructed.
 The larger circles show the how the overall state machine transitions.