[pwrmgr,ipgen] Fix hjson files

Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Oct 9, 2023 · 7215f8d · 7215f8d
1 parent 78c7edd
commit 7215f8d
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Showing 10 changed files with 13 additions and 20 deletions.
diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr_testplan.hjson b/hw/ip_templates/pwrmgr/data/pwrmgr_testplan.hjson
@@ -12,7 +12,7 @@
                      "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      // TODO: Top-level specific Hjson imported here. This will likely be resolved
                      // once we move to IPgen flow.
-                     "hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson"]
+                     "pwrmgr_sec_cm_testplan.hjson"]
   testpoints: [
     {
       name: smoke

diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -18,10 +18,7 @@
   fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1
 
   // Testplan hjson file.
-  testplan: "{proj_root}/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson"
-
-  // RAL spec - used to generate the RAL model.
-  ral_spec: "{proj_root}/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson"
+  testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
@@ -42,7 +39,7 @@
   ]
 
   // Exclusion files
-  vcs_cov_excl_files: ["{proj_root}/hw/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el"]
+  vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"]
 
   // Add additional tops for simulation.
   sim_tops: ["pwrmgr_bind",

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2673,7 +2673,7 @@
         Aon
         "0"
       ]
-      attr: templated
+      attr: ipgen
       clock_connections:
       {
         clk_i: clkmgr_aon_clocks.clk_io_div4_powerup

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -384,8 +384,7 @@
       },
       domain: ["Aon", "0"],
       base_addr: "0x40400000",
-      attr: "templated",
-
+      attr: "ipgen",
     },
     { name: "rstmgr_aon",
       type: "rstmgr",

diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -44,7 +44,6 @@
              "{proj_root}/hw/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson",
              "{proj_root}/hw/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson",
              "{proj_root}/hw/ip/pwm/dv/pwm_sim_cfg.hjson",
-             "{proj_root}/hw/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson",
              "{proj_root}/hw/ip/rom_ctrl/dv/rom_ctrl_sim_cfg.hjson",
              "{proj_root}/hw/ip/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson",
              "{proj_root}/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson",
@@ -59,6 +58,7 @@
              "{proj_root}/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson",
              // Top level IPs.
              "{proj_root}/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson",
+             "{proj_root}/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson",
              "{proj_root}/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson",
              "{proj_root}/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
              // Top level.

diff --git a/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson b/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson
@@ -153,7 +153,7 @@
                dut: pwrmgr
                fusesoc_core: lowrisc:dv:pwrmgr_sva
                import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
-               rel_path: "hw/ip/pwrmgr/{sub_flow}/{tool}"
+               rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/{sub_flow}/{tool}"
                overrides: [
                  {
                    name:  design_level
@@ -281,7 +281,7 @@
                dut: pwrmgr
                fusesoc_core: lowrisc:dv:pwrmgr_sva
                import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
-               rel_path: "hw/ip/pwrmgr/{sub_flow}/{tool}"
+               rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/{sub_flow}/{tool}"
                overrides: [
                  {
                    name:  design_level

diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson
@@ -12,7 +12,7 @@
                      "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
                      // TODO: Top-level specific Hjson imported here. This will likely be resolved
                      // once we move to IPgen flow.
-                     "hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson"]
+                     "pwrmgr_sec_cm_testplan.hjson"]
   testpoints: [
     {
       name: smoke

diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -18,10 +18,7 @@
   fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1
 
   // Testplan hjson file.
-  testplan: "{proj_root}/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson"
-
-  // RAL spec - used to generate the RAL model.
-  ral_spec: "{proj_root}/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson"
+  testplan: "{self_dir}/../data/pwrmgr_testplan.hjson"
 
   // Import additional common sim cfg files.
   import_cfgs: [// Project wide common sim cfg file
@@ -42,7 +39,7 @@
   ]
 
   // Exclusion files
-  vcs_cov_excl_files: ["{proj_root}/hw/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el"]
+  vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"]
 
   // Add additional tops for simulation.
   sim_tops: ["pwrmgr_bind",

diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
@@ -133,7 +133,7 @@
              {    name: pwrmgr
                   fusesoc_core: lowrisc:dv:pwrmgr_sim
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
-                  rel_path: "hw/ip/pwrmgr/dv/lint/{tool}"
+                  rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/dv/lint/{tool}"
              },
              {    name: rom_ctrl
                   fusesoc_core: lowrisc:dv:rom_ctrl_sim

diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -177,7 +177,7 @@
              {    name: pwrmgr
                   fusesoc_core: lowrisc:ip:pwrmgr
                   import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
-                  rel_path: "hw/ip/pwrmgr/lint/{tool}",
+                  rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/lint/{tool}",
                   overrides: [
                     {
                       name: design_level