[sival,pwrmgr] Clarify chip_sw_pwrmgr_sysrst_ctrl_reset testpoint

The previous description was inaccurate. Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Nov 29, 2023 · 1f5d71a · 1f5d71a
1 parent d452c94
commit 1f5d71a
Showing 1 changed file with 12 additions and 11 deletions.
diff --git a/hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson
@@ -375,26 +375,27 @@
     }
     {
       name: chip_sw_pwrmgr_sysrst_ctrl_reset
-      desc: '''Verify the effect of a sysrst_ctrl output in main power rail.
+      desc: '''Verify sysrst_ctrl and watchdog reset.
 
             - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset
               phase.
-            - After sysrst reset is generated by forcing, read the reset cause register in rstmgr to
-              confirm that the SW is now in the sysrst reset phase.
             - Generate sysrst by driving input PAD.
-            - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
-              the sysrst reset phase.
-            - Program the AON timer wdog to 'bark' after some time.
-            - Let the bark escalate to bite, which should result in a reset request.
-            - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
-              the wdog reset phase.
+            - After reset read the rstmgr reset_info CSR to confirm it indicates a sysrst reset.
             - Program the AON timer wdog to 'bark' after some time.
+            - Let the bark escalate to bite, which should cause a reset.
+            - After reset, read the rstmgr reset_info CSR to confirm it indicates a watchdog reset.
             SiVal: The pin that causes sysrst to reset needs to be pulsed from the host side.
+            The chip_sw_all_resets is a superset of this testpoint.
             '''
       stage: V2
       si_stage: None
-      tests: ["chip_sw_pwrmgr_sysrst_ctrl_reset"]
-      bazel: []
+      tests: [
+        "chip_sw_pwrmgr_sysrst_ctrl_reset",
+        "chip_sw_pwrmgr_all_reset_reqs",
+      ]
+      bazel: [
+        "//sw/device/tests:pwrmgr_all_reset_reqs_test_fpga_cw310_test_rom",
+      ]
     }
     {
       name: chip_sw_pwrmgr_b2b_sleep_reset_req