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[dv,py] Tweak ISS linker arg construction for Xcelium #2209

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hcallahan-lowrisc
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The previous code here was a bit too hacky, so implement a solution that directly follows the suggestion in the Cadence support article. An example was also added to make it clear what this transformation is achieving.

Additionally, cleanup some of the other code in the module, renaming for clarity and adding comments. Move some variable declarations around to be closer to their use. Add some more typehints.

Fixes #2205

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This drops the

dv/uvm/core_ibex/scripts/compile_tb.py Outdated Show resolved Hide resolved
The previous code here was a bit too hacky, so implement a solution that
directly follows the suggestion in the Cadence support article.
An example was also added to make it clear what this transformation is
achieving.

Add some more typehints, and cleanup names.

Signed-off-by: Harry Callahan <[email protected]>
Add comments, and move some variable declarations around to be closer to their use.

Signed-off-by: Harry Callahan <[email protected]>
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@rswarbrick rswarbrick left a comment

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Looks sensible to me!

@hcallahan-lowrisc
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Thanks!

@hcallahan-lowrisc hcallahan-lowrisc added this pull request to the merge queue Oct 1, 2024
Merged via the queue into lowRISC:master with commit fb49826 Oct 1, 2024
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@hcallahan-lowrisc hcallahan-lowrisc deleted the core_ibex_dv_xcelium_iss_flags branch October 2, 2024 10:05
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Compile_tb.py generate options not recogised by xrun
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