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[DAGCombine] Transform shl X, cttz(Y) to mul (Y & -Y), X if cttz is unsupported #85066

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May 29, 2024
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[DAGCombine] Transform shl X, cttz(Y) to mul (Y & -Y), X if cttz is unsupported #85066

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2bd2403
[DAGCombine] Add pre-commit tests. NFC.
dtcxzyw Mar 22, 2024
de06d42
[DAGCombine] Transform `shl X, cttz(Y)` to `mul (Y & -Y), X` if cttz …
dtcxzyw Mar 22, 2024
728dad3
[DAGCombine] Address review comments
dtcxzyw Apr 11, 2024
dad17f1
Merge branch 'main' into perf/shl-cttz-to-mul-lsb
dtcxzyw Apr 22, 2024
c11644b
[DAGCombiner] Address review comments. NFC.
dtcxzyw Apr 22, 2024
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12 changes: 12 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9985,6 +9985,18 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (SDValue NewSHL = visitShiftByConstant(N))
return NewSHL;

// fold (shl X, cttz(Y)) -> (mul (Y & -Y), X) if cttz is unsupported on the
// target.
if ((N1.getOpcode() == ISD::CTTZ || N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, VT) &&
TLI.isOperationLegalOrCustom(ISD::MUL, VT)) {
SDValue Y = N1.getOperand(0);
SDLoc DL(N);
SDValue NegY = DAG.getNegative(Y, DL, VT);
SDValue And = DAG.getNode(ISD::AND, DL, VT, Y, NegY);
return DAG.getNode(ISD::MUL, DL, VT, And, N0);
}

if (SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);

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