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[Hexagon] Optimize post-increment load and stores in loops. #82418

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merged 1 commit into from
Feb 22, 2024

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sgundapa
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This patch optimizes the post-increment instructions so that we can packetize them together.
v1 = phi(v0, v3')
v2,v3 = post_load v1, 4
v2',v3'= post_load v3, 4

This can be optimized in two ways

v1 = phi(v0, v3')
v2,v3' = post_load v1, 8
v2' = load v1, 4

@sgundapa sgundapa marked this pull request as ready for review February 20, 2024 21:17
@sgundapa
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One of the issues that was exposed with this patch is fixed here : #82386

@sgundapa sgundapa force-pushed the postinc_new branch 4 times, most recently from 2f40a7c to 52d7dcd Compare February 21, 2024 17:10
This patch optimizes the post-increment instructions so that
we can packetize them together.
v1 = phi(v0, v3')
v2,v3  = post_load v1, 4
v2',v3'= post_load v3, 4

This can be optimized in two ways

v1 = phi(v0, v3')
v2,v3' = post_load v1, 8
v2' = load v1, 4
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@SundeepKushwaha SundeepKushwaha left a comment

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lgtm

@sgundapa sgundapa merged commit d62ca8d into llvm:main Feb 22, 2024
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@sgundapa sgundapa deleted the postinc_new branch February 22, 2024 23:31
@steven-johnson
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This appears to have injected a failure in HVX codegen in Halide, e.g.

Hexagon simulator executed function 0x5c4a0 in 1000 cycles
Hexagon simulator executed function 0x614a0 in 1000 cycles
Hexagon simulator executed function 0x644c0 in 1000 cycles
Hexagon simulator executed function 0x88570 in 1000 cycles
CRASH from thread 0!
I think the exception was: 0x20, Misaligned Load @ 0x6
Register Dump (r0 clobbered, pc subject to prior action by the exception handler):
r00=000000cd r01=00002170 r02=00060b00 r03=00000000
r04=00000000 r05=00000000 r06=00060ff8 r07=00059b00
r08=00059b00 r09=00059900 r10=00000000 r11=00000000
r12=00000000 r13=00000000 r14=00089024 r15=00000000
r16=00000000 r17=00000000 r18=0005e800 r19=000021e0
r20=00058008 r21=00063b00 r22=babebeef r23=babebeef
r24=babebeef r25=babebeef r26=babebeef r27=babebeef
r28=0004ada0 r29=04159598 r30=041595a0 r31=00012448
sa0=00088400 lc0=00000001 sa1=00000000 lc1=00000000
p30=0000ff00  m0=00000000  m1=00000000 usr=00010000
 pc=00001b3c ugp=00000000  gp=00058000 elr=00022908
badva0=00000006 badva1=041595f0
ssr=80140020 ccr=00130000 tid=00000000 imask=00000000
evb=000000cd modectl=00002170 syscfg=00060b00 ipend=00000000

@steven-johnson
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Ping -- this is still broken. Is a fix (or rollback) on the way? Can we assist in some way?

@sgundapa
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sgundapa commented Feb 26, 2024 via email

@sgundapa
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Please feel free to revert the change meanwhile.

@steven-johnson
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I don't have the privileges to revert this, but if you do so I will offer my approval :-)

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steven-johnson commented Feb 26, 2024 via email

@sgundapa
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#83151 - to revert the change.

sgundapa pushed a commit that referenced this pull request Feb 27, 2024
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3 participants