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[AArch64] Reland merge index address with large offset into base address #79951

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merged 2 commits into from
Aug 15, 2024
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[AArch64] Reland merge index address with large offset into base address #79951

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3319049
[AArch64] merge index address with large offset into base address
vfdff Nov 10, 2023
43ffe2e
[AArch64] Fold more load.x into load.i with large offset
vfdff Dec 18, 2023
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23 changes: 23 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4516,6 +4516,29 @@ AArch64InstrInfo::getLdStOffsetOp(const MachineInstr &MI) {
return MI.getOperand(Idx);
}

const MachineOperand &
AArch64InstrInfo::getLdStAmountOp(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
llvm_unreachable("Unexpected opcode");
case AArch64::LDRBroX:
case AArch64::LDRBBroX:
case AArch64::LDRSBXroX:
case AArch64::LDRSBWroX:
case AArch64::LDRHroX:
case AArch64::LDRHHroX:
case AArch64::LDRSHXroX:
case AArch64::LDRSHWroX:
case AArch64::LDRWroX:
case AArch64::LDRSroX:
case AArch64::LDRSWroX:
case AArch64::LDRDroX:
case AArch64::LDRXroX:
case AArch64::LDRQroX:
return MI.getOperand(4);
}
}

static const TargetRegisterClass *getRegClass(const MachineInstr &MI,
Register Reg) {
if (MI.getParent() == nullptr)
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.h
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Expand Up @@ -254,6 +254,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
/// Returns whether the physical register is FP or NEON.
static bool isFpOrNEON(Register Reg);

/// Returns the shift amount operator of a load/store.
static const MachineOperand &getLdStAmountOp(const MachineInstr &MI);

/// Returns whether the instruction is FP or NEON.
static bool isFpOrNEON(const MachineInstr &MI);

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