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[VPlan] Remove loop region in optimizeForVFAndUF. #108378

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d3614bc
[VPlan] Use ResumePhi to create reduction resume phis.
fhahn Sep 25, 2024
5f8fabe
[VPlan] Remove loop region in optimizeForVFAndUF.
fhahn Sep 25, 2024
c68ddd1
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Nov 2, 2024
f0421c6
!fixup after merge
fhahn Nov 4, 2024
4a0eb12
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Nov 4, 2024
9499aaa
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Nov 4, 2024
a4843b5
!fixup address latest comments, thanks!
fhahn Nov 4, 2024
f5d2bc6
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Nov 9, 2024
1222e23
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Nov 24, 2024
706b681
!fixup address latest comments, thanks!
fhahn Nov 24, 2024
71436fc
!fixup fix formatting
fhahn Nov 24, 2024
38cbdf6
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 7, 2024
cc43362
!fixup update after merge.
fhahn Dec 7, 2024
e758945
!fixup remove unrelated changes.
fhahn Dec 7, 2024
d4e8c7e
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 17, 2024
1d4b2e6
!fixup partial fixup after merging main.
fhahn Dec 17, 2024
98529f3
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 23, 2024
0c76e9d
!fixup update on top of current main, iterate to find vector.ph
fhahn Dec 23, 2024
dd45cad
[VPlan] Manage created blocks directly in VPlan. (NFC)
fhahn Dec 18, 2024
e72a71f
!fixup address comments, add comments
fhahn Dec 24, 2024
407dbc1
[VPlan] Funnel
fhahn Dec 27, 2024
af48fcc
[VPlan] Funnel
fhahn Dec 27, 2024
f51412a
Merge remote-tracking branch 'origin/main' into manage-blocks-in-vplan
fhahn Dec 27, 2024
f2b5e53
Merge remote-tracking branch 'origin/main' into manage-blocks-in-vplan
fhahn Dec 28, 2024
1f4febc
Merge branch 'manage-blocks-in-vplan' into vplan-remove-loop-region-i…
fhahn Dec 28, 2024
3d412a1
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 31, 2024
56a4181
!fixup update after merge
fhahn Dec 31, 2024
88fcf60
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 31, 2024
303ce93
!fixup adjust assert
fhahn Dec 31, 2024
3f016cb
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 31, 2024
430c369
Merge remote-tracking branch 'origin/main' into vplan-remove-loop-reg…
fhahn Dec 31, 2024
f9db2d0
!fixup update extra tests.
fhahn Dec 31, 2024
cabc591
!fixup fix formatting
fhahn Dec 31, 2024
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74 changes: 42 additions & 32 deletions llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2383,12 +2383,12 @@ void InnerLoopVectorizer::scalarizeInstruction(const Instruction *Instr,
// End if-block.
VPRegionBlock *Parent = RepRecipe->getParent()->getParent();
bool IfPredicateInstr = Parent ? Parent->isReplicator() : false;
assert((Parent || all_of(RepRecipe->operands(),
[](VPValue *Op) {
return Op->isDefinedOutsideLoopRegions();
})) &&
"Expected a recipe is either within a region or all of its operands "
"are defined outside the vectorized region.");
assert(
(Parent || !RepRecipe->getParent()->getPlan()->getVectorLoopRegion() ||
all_of(RepRecipe->operands(),
[](VPValue *Op) { return Op->isDefinedOutsideLoopRegions(); })) &&
"Expected a recipe is either within a region or all of its operands "
"are defined outside the vectorized region.");
if (IfPredicateInstr)
PredicatedInstructions.push_back(Cloned);
}
Expand Down Expand Up @@ -2448,6 +2448,8 @@ InnerLoopVectorizer::getOrCreateVectorTripCount(BasicBlock *InsertBlock) {
/// scalar preheader.
static void introduceCheckBlockInVPlan(VPlan &Plan, BasicBlock *CheckIRBB) {
VPBlockBase *ScalarPH = Plan.getScalarPreheader();
// FIXME: Cannot get the vector preheader at the moment if the vector loop
// region has been removed.
VPBlockBase *VectorPH = Plan.getVectorPreheader();
VPBlockBase *PreVectorPH = VectorPH->getSinglePredecessor();
if (PreVectorPH->getNumSuccessors() != 1) {
Expand Down Expand Up @@ -2988,6 +2990,9 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) {
getOrCreateVectorTripCount(nullptr), LoopMiddleBlock, State);
}

if (!State.Plan->getVectorLoopRegion())
return;

for (Instruction *PI : PredicatedInstructions)
sinkScalarOperands(&*PI);

Expand Down Expand Up @@ -7790,24 +7795,25 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
makeFollowupLoopID(OrigLoopID, {LLVMLoopVectorizeFollowupAll,
LLVMLoopVectorizeFollowupVectorized});

VPBasicBlock *HeaderVPBB =
BestVPlan.getVectorLoopRegion()->getEntryBasicBlock();
Loop *L = LI->getLoopFor(State.CFG.VPBB2IRBB[HeaderVPBB]);
if (VectorizedLoopID)
L->setLoopID(*VectorizedLoopID);
else {
// Keep all loop hints from the original loop on the vector loop (we'll
// replace the vectorizer-specific hints below).
if (MDNode *LID = OrigLoop->getLoopID())
L->setLoopID(LID);

LoopVectorizeHints Hints(L, true, *ORE);
Hints.setAlreadyVectorized();
if (auto *R = BestVPlan.getVectorLoopRegion()) {
VPBasicBlock *HeaderVPBB = R->getEntryBasicBlock();
Loop *L = LI->getLoopFor(State.CFG.VPBB2IRBB[HeaderVPBB]);
if (VectorizedLoopID) {
L->setLoopID(*VectorizedLoopID);
} else {
// Keep all loop hints from the original loop on the vector loop (we'll
// replace the vectorizer-specific hints below).
if (MDNode *LID = OrigLoop->getLoopID())
L->setLoopID(LID);

LoopVectorizeHints Hints(L, true, *ORE);
Hints.setAlreadyVectorized();
}
TargetTransformInfo::UnrollingPreferences UP;
TTI.getUnrollingPreferences(L, *PSE.getSE(), UP, ORE);
if (!UP.UnrollVectorizedLoop || VectorizingEpilogue)
addRuntimeUnrollDisableMetaData(L);
}
TargetTransformInfo::UnrollingPreferences UP;
TTI.getUnrollingPreferences(L, *PSE.getSE(), UP, ORE);
if (!UP.UnrollVectorizedLoop || VectorizingEpilogue)
addRuntimeUnrollDisableMetaData(L);

// 3. Fix the vectorized code: take care of header phi's, live-outs,
// predication, updating analyses.
Expand All @@ -7816,15 +7822,19 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
ILV.printDebugTracesAtEnd();

// 4. Adjust branch weight of the branch in the middle block.
auto *MiddleTerm =
cast<BranchInst>(State.CFG.VPBB2IRBB[ExitVPBB]->getTerminator());
if (MiddleTerm->isConditional() &&
hasBranchWeightMD(*OrigLoop->getLoopLatch()->getTerminator())) {
// Assume that `Count % VectorTripCount` is equally distributed.
unsigned TripCount = BestVPlan.getUF() * State.VF.getKnownMinValue();
assert(TripCount > 0 && "trip count should not be zero");
const uint32_t Weights[] = {1, TripCount - 1};
setBranchWeights(*MiddleTerm, Weights, /*IsExpected=*/false);
if (auto *R = BestVPlan.getVectorLoopRegion()) {
auto *ExitVPBB = cast<VPBasicBlock>(R->getSingleSuccessor());

auto *MiddleTerm =
cast<BranchInst>(State.CFG.VPBB2IRBB[ExitVPBB]->getTerminator());
if (MiddleTerm->isConditional() &&
hasBranchWeightMD(*OrigLoop->getLoopLatch()->getTerminator())) {
// Assume that `Count % VectorTripCount` is equally distributed.
unsigned TripCount = BestVPlan.getUF() * State.VF.getKnownMinValue();
assert(TripCount > 0 && "trip count should not be zero");
const uint32_t Weights[] = {1, TripCount - 1};
setBranchWeights(*MiddleTerm, Weights, /*IsExpected=*/false);
}
}

return State.ExpandedSCEVs;
Expand Down
115 changes: 63 additions & 52 deletions llvm/lib/Transforms/Vectorize/VPlan.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -447,7 +447,6 @@ void VPBasicBlock::connectToPredecessors(VPTransformState::CFGState &CFG) {
CFG.DTU.applyUpdates({{DominatorTree::Insert, PredBB, NewBB}});
}
}

void VPIRBasicBlock::execute(VPTransformState *State) {
assert(getHierarchicalSuccessors().size() <= 2 &&
"VPIRBasicBlock can have at most two successors at the moment!");
Expand Down Expand Up @@ -487,7 +486,7 @@ void VPBasicBlock::execute(VPTransformState *State) {
};

// 1. Create an IR basic block.
if (this == getPlan()->getVectorPreheader() ||
if (this == getPlan()->getEntry() ||
(Replica && this == getParent()->getEntry()) ||
IsReplicateRegion(getSingleHierarchicalPredecessor())) {
// Reuse the previous basic block if the current VPBB is either
Expand Down Expand Up @@ -557,7 +556,7 @@ VPBasicBlock *VPBasicBlock::splitAt(iterator SplitAt) {
template <typename T> static T *getEnclosingLoopRegionForRegion(T *P) {
if (P && P->isReplicator()) {
P = P->getParent();
assert(!cast<VPRegionBlock>(P)->isReplicator() &&
assert((!P || !cast<VPRegionBlock>(P)->isReplicator()) &&
"unexpected nested replicate regions");
}
return P;
Expand Down Expand Up @@ -936,7 +935,6 @@ void VPlan::prepareToExecute(Value *TripCountV, Value *VectorTripCountV,

IRBuilder<> Builder(State.CFG.PrevBB->getTerminator());
// FIXME: Model VF * UF computation completely in VPlan.
assert(VFxUF.getNumUsers() && "VFxUF expected to always have users");
unsigned UF = getUF();
if (VF.getNumUsers()) {
Value *RuntimeVF = getRuntimeVF(Builder, TCTy, State.VF);
Expand Down Expand Up @@ -1015,49 +1013,51 @@ void VPlan::execute(VPTransformState *State) {
for (VPBlockBase *Block : RPOT)
Block->execute(State);

VPBasicBlock *LatchVPBB = getVectorLoopRegion()->getExitingBasicBlock();
BasicBlock *VectorLatchBB = State->CFG.VPBB2IRBB[LatchVPBB];

// Fix the latch value of canonical, reduction and first-order recurrences
// phis in the vector loop.
VPBasicBlock *Header = getVectorLoopRegion()->getEntryBasicBlock();
for (VPRecipeBase &R : Header->phis()) {
// Skip phi-like recipes that generate their backedege values themselves.
if (isa<VPWidenPHIRecipe>(&R))
continue;

if (isa<VPWidenInductionRecipe>(&R)) {
PHINode *Phi = nullptr;
if (isa<VPWidenIntOrFpInductionRecipe>(&R)) {
Phi = cast<PHINode>(State->get(R.getVPSingleValue()));
} else {
auto *WidenPhi = cast<VPWidenPointerInductionRecipe>(&R);
assert(!WidenPhi->onlyScalarsGenerated(State->VF.isScalable()) &&
"recipe generating only scalars should have been replaced");
auto *GEP = cast<GetElementPtrInst>(State->get(WidenPhi));
Phi = cast<PHINode>(GEP->getPointerOperand());
}
if (auto *LoopRegion = getVectorLoopRegion()) {
VPBasicBlock *LatchVPBB = LoopRegion->getExitingBasicBlock();
BasicBlock *VectorLatchBB = State->CFG.VPBB2IRBB[LatchVPBB];

Phi->setIncomingBlock(1, VectorLatchBB);
// Fix the latch value of canonical, reduction and first-order recurrences
// phis in the vector loop.
VPBasicBlock *Header = LoopRegion->getEntryBasicBlock();
for (VPRecipeBase &R : Header->phis()) {
// Skip phi-like recipes that generate their backedege values themselves.
if (isa<VPWidenPHIRecipe>(&R))
continue;

// Move the last step to the end of the latch block. This ensures
// consistent placement of all induction updates.
Instruction *Inc = cast<Instruction>(Phi->getIncomingValue(1));
Inc->moveBefore(VectorLatchBB->getTerminator()->getPrevNode());
if (isa<VPWidenInductionRecipe>(&R)) {
PHINode *Phi = nullptr;
if (isa<VPWidenIntOrFpInductionRecipe>(&R)) {
Phi = cast<PHINode>(State->get(R.getVPSingleValue()));
} else {
auto *WidenPhi = cast<VPWidenPointerInductionRecipe>(&R);
assert(!WidenPhi->onlyScalarsGenerated(State->VF.isScalable()) &&
"recipe generating only scalars should have been replaced");
auto *GEP = cast<GetElementPtrInst>(State->get(WidenPhi));
Phi = cast<PHINode>(GEP->getPointerOperand());
}

Phi->setIncomingBlock(1, VectorLatchBB);

// Move the last step to the end of the latch block. This ensures
// consistent placement of all induction updates.
Instruction *Inc = cast<Instruction>(Phi->getIncomingValue(1));
Inc->moveBefore(VectorLatchBB->getTerminator()->getPrevNode());

// Use the steps for the last part as backedge value for the induction.
if (auto *IV = dyn_cast<VPWidenIntOrFpInductionRecipe>(&R))
Inc->setOperand(0, State->get(IV->getLastUnrolledPartOperand()));
continue;
}

// Use the steps for the last part as backedge value for the induction.
if (auto *IV = dyn_cast<VPWidenIntOrFpInductionRecipe>(&R))
Inc->setOperand(0, State->get(IV->getLastUnrolledPartOperand()));
continue;
auto *PhiR = cast<VPHeaderPHIRecipe>(&R);
bool NeedsScalar = isa<VPScalarPHIRecipe>(PhiR) ||
(isa<VPReductionPHIRecipe>(PhiR) &&
cast<VPReductionPHIRecipe>(PhiR)->isInLoop());
Value *Phi = State->get(PhiR, NeedsScalar);
Value *Val = State->get(PhiR->getBackedgeValue(), NeedsScalar);
cast<PHINode>(Phi)->addIncoming(Val, VectorLatchBB);
}

auto *PhiR = cast<VPHeaderPHIRecipe>(&R);
bool NeedsScalar = isa<VPScalarPHIRecipe>(PhiR) ||
(isa<VPReductionPHIRecipe>(PhiR) &&
cast<VPReductionPHIRecipe>(PhiR)->isInLoop());
Value *Phi = State->get(PhiR, NeedsScalar);
Value *Val = State->get(PhiR->getBackedgeValue(), NeedsScalar);
cast<PHINode>(Phi)->addIncoming(Val, VectorLatchBB);
}

State->CFG.DTU.flush();
Expand All @@ -1069,19 +1069,28 @@ InstructionCost VPlan::cost(ElementCount VF, VPCostContext &Ctx) {
return getVectorLoopRegion()->cost(VF, Ctx);
}

VPBasicBlock *VPlan::getVectorPreheader() {
VPBlockBase *Current = getEntry()->getSuccessors().back();
while (Current->getNumSuccessors() == 2)
Current = Current->getSuccessors().back();
return cast<VPBasicBlock>(Current);
}

VPBasicBlock *VPlan::getVectorPreheader() const {
VPBlockBase *Current = getEntry()->getSuccessors().back();
while (Current->getNumSuccessors() == 2)
Current = Current->getSuccessors().back();
return cast<VPBasicBlock>(Current);
}

VPRegionBlock *VPlan::getVectorLoopRegion() {
// TODO: Cache if possible.
for (VPBlockBase *B : vp_depth_first_shallow(getEntry()))
if (auto *R = dyn_cast<VPRegionBlock>(B))
return R;
return nullptr;
return dyn_cast<VPRegionBlock>(getVectorPreheader()->getSingleSuccessor());
;
}

const VPRegionBlock *VPlan::getVectorLoopRegion() const {
for (const VPBlockBase *B : vp_depth_first_shallow(getEntry()))
if (auto *R = dyn_cast<VPRegionBlock>(B))
return R;
return nullptr;
return dyn_cast<VPRegionBlock>(getVectorPreheader()->getSingleSuccessor());
}

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
Expand Down Expand Up @@ -1427,8 +1436,10 @@ void VPlanIngredient::print(raw_ostream &O) const {
#endif

bool VPValue::isDefinedOutsideLoopRegions() const {

return !hasDefiningRecipe() ||
!getDefiningRecipe()->getParent()->getEnclosingLoopRegion();
(!getDefiningRecipe()->getParent()->getEnclosingLoopRegion() &&
getDefiningRecipe()->getParent()->getPlan()->getVectorLoopRegion());
}

void VPValue::replaceAllUsesWith(VPValue *New) {
Expand Down
7 changes: 2 additions & 5 deletions llvm/lib/Transforms/Vectorize/VPlan.h
Original file line number Diff line number Diff line change
Expand Up @@ -3668,8 +3668,6 @@ class VPRegionBlock : public VPBlockBase {
const VPBlockBase *getEntry() const { return Entry; }
VPBlockBase *getEntry() { return Entry; }

/// Set \p EntryBlock as the entry VPBlockBase of this VPRegionBlock. \p
/// EntryBlock must have no predecessors.
void setEntry(VPBlockBase *EntryBlock) {
assert(EntryBlock->getPredecessors().empty() &&
"Entry block cannot have predecessors.");
Expand Down Expand Up @@ -3845,9 +3843,8 @@ class VPlan {
const VPBasicBlock *getEntry() const { return Entry; }

/// Returns the preheader of the vector loop region.
VPBasicBlock *getVectorPreheader() {
return cast<VPBasicBlock>(getVectorLoopRegion()->getSinglePredecessor());
}
VPBasicBlock *getVectorPreheader();
VPBasicBlock *getVectorPreheader() const;

/// Returns the VPRegionBlock of the vector loop.
VPRegionBlock *getVectorLoopRegion();
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2376,7 +2376,9 @@ void VPBranchOnMaskRecipe::execute(VPTransformState &State) {
// Replace the temporary unreachable terminator with a new conditional branch,
// whose two destinations will be set later when they are created.
auto *CurrentTerminator = State.CFG.PrevBB->getTerminator();
assert(isa<UnreachableInst>(CurrentTerminator) &&
assert((isa<UnreachableInst>(CurrentTerminator) ||
(isa<BranchInst>(CurrentTerminator) &&
!CurrentTerminator->getOperand(0))) &&
"Expected to replace unreachable terminator with conditional branch.");
auto *CondBr = BranchInst::Create(State.CFG.PrevBB, nullptr, ConditionBit);
CondBr->setSuccessor(0, nullptr);
Expand Down
57 changes: 43 additions & 14 deletions llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -794,11 +794,14 @@ static void simplifyRecipe(VPRecipeBase &R, VPTypeAnalysis &TypeInfo) {
return R.getVPSingleValue()->replaceAllUsesWith(R.getOperand(1));
}

/// Try to simplify the recipes in \p Plan
static void simplifyRecipes(VPlan &Plan) {
/// Try to simplify the recipes in \p Plan. If \p CanonicalIVTy is not nullptr,
/// use it directly instead of retrieving the canonical IV type from the plan
/// which may not exist any longer.
static void simplifyRecipes(VPlan &Plan, Type *CanonicalIVTy = nullptr) {
ReversePostOrderTraversal<VPBlockDeepTraversalWrapper<VPBlockBase *>> RPOT(
Plan.getEntry());
Type *CanonicalIVType = Plan.getCanonicalIV()->getScalarType();
Type *CanonicalIVType =
CanonicalIVTy ? CanonicalIVTy : Plan.getCanonicalIV()->getScalarType();
VPTypeAnalysis TypeInfo(CanonicalIVType);
for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(RPOT)) {
for (VPRecipeBase &R : make_early_inc_range(*VPBB)) {
Expand All @@ -812,8 +815,8 @@ void VPlanTransforms::optimizeForVFAndUF(VPlan &Plan, ElementCount BestVF,
PredicatedScalarEvolution &PSE) {
assert(Plan.hasVF(BestVF) && "BestVF is not available in Plan");
assert(Plan.hasUF(BestUF) && "BestUF is not available in Plan");
VPBasicBlock *ExitingVPBB =
Plan.getVectorLoopRegion()->getExitingBasicBlock();
VPRegionBlock *VectorRegion = Plan.getVectorLoopRegion();
VPBasicBlock *ExitingVPBB = VectorRegion->getExitingBasicBlock();
auto *Term = &ExitingVPBB->back();
// Try to simplify the branch condition if TC <= VF * UF when preparing to
// execute the plan for the main vector loop. We only do this if the
Expand All @@ -837,16 +840,42 @@ void VPlanTransforms::optimizeForVFAndUF(VPlan &Plan, ElementCount BestVF,
!SE.isKnownPredicate(CmpInst::ICMP_ULE, TripCount, C))
return;

LLVMContext &Ctx = SE.getContext();
auto *BOC = new VPInstruction(
VPInstruction::BranchOnCond,
{Plan.getOrAddLiveIn(ConstantInt::getTrue(Ctx))}, Term->getDebugLoc());

SmallVector<VPValue *> PossiblyDead(Term->operands());
Term->eraseFromParent();
for (VPValue *Op : PossiblyDead)
recursivelyDeleteDeadRecipes(Op);
ExitingVPBB->appendRecipe(BOC);
auto *Header = cast<VPBasicBlock>(VectorRegion->getEntry());
auto *CanIVTy = Plan.getCanonicalIV()->getScalarType();
if (any_of(Header->phis(),
IsaPred<VPWidenIntOrFpInductionRecipe, VPReductionPHIRecipe>)) {
LLVMContext &Ctx = SE.getContext();
auto *BOC = new VPInstruction(
VPInstruction::BranchOnCond,
{Plan.getOrAddLiveIn(ConstantInt::getTrue(Ctx))}, Term->getDebugLoc());
ExitingVPBB->appendRecipe(BOC);
} else {
for (VPRecipeBase &R : make_early_inc_range(Header->phis())) {
auto *P = cast<VPHeaderPHIRecipe>(&R);
P->replaceAllUsesWith(P->getStartValue());
P->eraseFromParent();
}

VPBlockBase *Preheader = Plan.getVectorPreheader();
VPBlockBase *Middle = Plan.getMiddleBlock();
VPBlockUtils::disconnectBlocks(Preheader, VectorRegion);
VPBlockUtils::disconnectBlocks(VectorRegion, Middle);

Header->setParent(nullptr);
ExitingVPBB->setParent(nullptr);

for (VPBlockBase *B : vp_depth_first_shallow(VectorRegion->getEntry())) {
if (isa<VPRegionBlock>(B))
B->setParent(nullptr);
}
VPBlockUtils::connectBlocks(Preheader, Header);
VPBlockUtils::connectBlocks(ExitingVPBB, Middle);
simplifyRecipes(Plan, CanIVTy);
}

VPlanTransforms::removeDeadRecipes(Plan);

Plan.setVF(BestVF);
Plan.setUF(BestUF);
// TODO: Further simplifications are possible
Expand Down
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