PR for llvm/llvm-project#64794 #768
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If we start with an i128 shift, the initial shift amount would usually have zeros in bit 8 and above. xoring the shift amount with -1 will set those upper bits to 1. If DAGCombiner is able to prove those bits are now 1, then the shift that uses the xor will be replaced with undef. Which we don't want. Reduce the xor constant to VT.bits-1 where VT is half the size of the larger shift type. This avoids toggling the upper bits. The hardware shift instruction only uses the lower bits of the shift amount. I assume the code used NOT because the hardware doesn't use the upper bits, but that isn't compatible with the LLVM poison semantics. Fixes #71142. (cherry picked from commit 8d24d3900ec3f28902b2fad4a2c2c2b789257424)
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@nikic ok to backport? |
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LGTM |
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resolves llvm/llvm-project#64794