Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

PR for llvm/llvm-project#70208 #763

Merged
merged 1 commit into from
Nov 13, 2023
Merged

PR for llvm/llvm-project#70208 #763

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1000,6 +1000,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTEND_VECTOR_INREG(SDNode *N);
SDValue WidenVecOp_STORE(SDNode* N);
SDValue WidenVecOp_VP_STORE(SDNode *N, unsigned OpNo);
SDValue WidenVecOp_VP_STRIDED_STORE(SDNode *N, unsigned OpNo);
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5946,6 +5946,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
Res = WidenVecOp_VP_STRIDED_STORE(N, OpNo);
break;
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
Res = WidenVecOp_EXTEND_VECTOR_INREG(N);
break;
case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break;
case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
Expand Down Expand Up @@ -6338,6 +6343,11 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
N->getValueType(0), InOp, N->getOperand(1));
}

SDValue DAGTypeLegalizer::WidenVecOp_EXTEND_VECTOR_INREG(SDNode *N) {
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), InOp);
}

SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
// We have to widen the value, but we want only to store the original
// vector type.
Expand Down
25 changes: 25 additions & 0 deletions llvm/test/CodeGen/PowerPC/pr70208.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s

define <4 x i64> @widget(<8 x i16> %call) {
; CHECK-LABEL: widget:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: xxlxor 37, 37, 37
; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: addi 3, 4, .LCPI0_1@toc@l
; CHECK-NEXT: lxvd2x 1, 0, 3
; CHECK-NEXT: xxswapd 35, 0
; CHECK-NEXT: xxswapd 32, 1
; CHECK-NEXT: vperm 4, 5, 2, 3
; CHECK-NEXT: vperm 3, 5, 2, 0
; CHECK-NEXT: vmr 2, 4
; CHECK-NEXT: blr
%bitcast = bitcast <8 x i16> %call to <16 x i8>
%shufflevector = shufflevector <16 x i8> <i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0>, <16 x i8> %bitcast, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 6, i32 7, i32 20, i32 21, i32 10, i32 11, i32 22, i32 23, i32 14, i32 15>
%bitcast1 = bitcast <16 x i8> %shufflevector to <4 x i32>
%zext = zext <4 x i32> %bitcast1 to <4 x i64>
ret <4 x i64> %zext
}
Loading