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[FIRRTL] Initial support for classes and objects in Dedup. #6582
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Original file line number | Diff line number | Diff line change |
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; RUN: firtool %s -ir-verilog | FileCheck %s | ||
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FIRRTL version 3.3.0 | ||
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circuit Test : %[[ | ||
{ | ||
"class": "firrtl.transforms.MustDeduplicateAnnotation", | ||
"modules": ["~Test|CPU_1", "~Test|CPU_2"] | ||
} | ||
]] | ||
; CHECK: hw.hierpath private [[NLA1:@.+]] [@Test::@sym, @CPU_1::[[SYM1:@.+]]] | ||
; CHECK: hw.hierpath private [[NLA2:@.+]] [@Test::@sym, @CPU_1::[[SYM2:@.+]], @Fetch_1::[[SYM3:@.+]]] | ||
module Test : | ||
input in : UInt<1> | ||
output out_1 : UInt<1> | ||
output out_2 : UInt<1> | ||
output om_out_1 : AnyRef | ||
output om_out_2 : AnyRef | ||
inst cpu_1 of CPU_1 | ||
inst cpu_2 of CPU_2 | ||
connect cpu_1.in, in | ||
connect cpu_2.in, in | ||
connect out_1, cpu_1.out | ||
connect out_2, cpu_2.out | ||
propassign om_out_1, cpu_1.om_out | ||
propassign om_out_2, cpu_2.om_out | ||
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; CHECK-LABEL: hw.module private @CPU_1 | ||
; CHECK-SAME: out out : i1 {hw.exportPort = #hw<innerSym[[SYM1]]>} | ||
module CPU_1 : | ||
input in : UInt<1> | ||
output out : UInt<1> | ||
output om_out : AnyRef | ||
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object om of OM_1 | ||
propassign om_out, om | ||
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; CHECK: hw.instance "fetch_1" sym [[SYM2]] | ||
inst fetch_1 of Fetch_1 | ||
inst fetch_2 of Fetch_1 | ||
connect fetch_1.in, in | ||
connect fetch_2.in, in | ||
connect out, fetch_1.out | ||
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; CHECK-NOT: CPU_2 | ||
module CPU_2 : | ||
input in : UInt<1> | ||
output out : UInt<1> | ||
output om_out : AnyRef | ||
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object om of OM_2 | ||
propassign om_out, om | ||
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inst fetch_1 of Fetch_2 | ||
inst fetch_2 of Fetch_2 | ||
connect fetch_1.in, in | ||
connect fetch_2.in, in | ||
connect out, fetch_1.out | ||
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module Fetch_1 : | ||
input in : UInt<1> | ||
output out : UInt<1> | ||
; CHECK: %foo = sv.wire sym [[SYM3]] | ||
wire foo : UInt<1> | ||
connect foo, in | ||
connect out, foo | ||
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; CHECK-NOT: Fetch_2 | ||
module Fetch_2 : | ||
input in : UInt<1> | ||
output out : UInt<1> | ||
wire foo : UInt<1> | ||
connect foo, in | ||
connect out, foo | ||
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class Foo_1 : | ||
skip | ||
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class Foo_2 : | ||
skip | ||
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; CHECK-LABEL: om.class @OM_1(%basepath: !om.basepath) | ||
class OM_1 : | ||
output out_1 : Path | ||
output out_2 : Path | ||
output out_foo_1 : Inst<Foo_1> | ||
output out_foo_2 : Inst<Foo_2> | ||
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object foo_1 of Foo_1 | ||
propassign out_foo_1, foo_1 | ||
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object foo_2 of Foo_2 | ||
propassign out_foo_2, foo_2 | ||
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; CHECK: om.path_create reference %basepath [[NLA1]] | ||
propassign out_1, path("OMReferenceTarget:~Test|CPU_1>out") | ||
; CHECK: om.path_create reference %basepath [[NLA2]] | ||
propassign out_2, path("OMReferenceTarget:~Test|CPU_1/fetch_1:Fetch_1>foo") | ||
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; CHECK-NOT: OM_2 | ||
class OM_2 : | ||
output out_1 : Path | ||
output out_2 : Path | ||
output out_foo_1 : Inst<Foo_1> | ||
output out_foo_2 : Inst<Foo_2> | ||
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object foo_1 of Foo_1 | ||
propassign out_foo_1, foo_1 | ||
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object foo_2 of Foo_2 | ||
propassign out_foo_2, foo_2 | ||
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propassign out_1, path("OMReferenceTarget:~Test|CPU_2>out") | ||
propassign out_2, path("OMReferenceTarget:~Test|CPU_2/fetch_1:Fetch_2>foo") |
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I think this part should be moved to
update(Type type)
to properly handle class types on ports.