Wiring problem error with const source and non-const sink w/no-ref-type option

[dtzSiFive]

Consider:

FIRRTL version 4.0.0

circuit ZW: %[[
  {
    "class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
    "keys": [
      {
        "class": "sifive.enterprise.grandcentral.ReferenceDataTapKey",
        "source": "~ZW|ZW>in",
        "sink": "~ZW|ZW/c:Child>sink"
      }
    ]
  }
]]
  module Child:
    wire sink : UInt<0>
    invalidate sink
 

  public module ZW:
    input in : const UInt<0>

    inst c of Child

Built with firtool --lower-annotations-no-ref-type-ports this produces an error:

tap_zw_const.fir:21:11: error: Wiring Problem source type '!firrtl.const.uint<0>' does not match sink type '!firrtl.uint<0>'
    input in : const UInt<0>
          ^
tap_zw_const.fir:16:5: note: The sink is here.
    wire sink : UInt<0>
    ^

cc #4651.