Bump LLVM

llvm · Sep 6, 2024 · fbf29e2 · fbf29e2
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diff --git a/integration_test/Bindings/Python/dialects/seq.py b/integration_test/Bindings/Python/dialects/seq.py
@@ -85,7 +85,7 @@ def top(module):
   # CHECK-LABEL: === Verilog ===
   print("=== Verilog ===")
 
-  pm = PassManager.parse("builtin.module(lower-seq-to-sv)")
+  pm = PassManager.parse("builtin.module(lower-seq-to-sv,canonicalize)")
   pm.run(m.operation)
   # CHECK: always_ff @(posedge clk)
   # CHECK: my_reg <= {{.+}}

diff --git a/llvm b/llvm