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VLSI_proeject
VLSI_proeject PublicThis frequency divider is able to divide the clock signal depending on 3-bit input signal. Also, we were required to draw block diagrams to represent the structure, use “laker” to layout, use anoth…
SourcePawn 1
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AIC_project
AIC_project PublicWe were required to design a "fully differential OpAmp" with some analysis, including open-loop gain ones and closed-loop ones in common-mode and differential-mode. Moreover, we simulated it with D…
SourcePawn 1
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Logic_Design_final
Logic_Design_final PublicWe desired to use FPGA board with other peripheral devices to accomplish this game. For instance, we use bottoms to control the moving direction of snake, use seven segment display to show the time…
Verilog
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Probability_final_project
Probability_final_project PublicIn this project, we wanted to know the relationship between restaurant chosen and gender, weekday. To analyze it, we designed a program to do the cross validation, and we represented the result wit…
Python
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Statistics_final
Statistics_final PublicThis project is purely a practice of using "R" to analyze the problem, and we take the data from SRDA of Academia Sinica.
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download_video
download_video PublicDownload the video from YouTube and rename to the name we want.
Jupyter Notebook
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