Update doc

doc/sphinx/changelog.rst

@@ -144,6 +144,7 @@
 
   .. note::
 
+    * `LIEF extended <https://extended.lief.re>`_ is now open to everyone
     * C++ SDK is now available
     * Rust package is now available
 

doc/sphinx/extended/disassembler/index.rst

@@ -114,6 +114,62 @@ Thus, you can write:
 
    You can also check the assembler documentation here: :ref:`Assembler <extended-assembler>`
 
+For the architectures ``x86/x86-64`` and ``AArch64`` one can also iterate over
+the instruction's operands:
+
+.. tabs::
+
+   .. tab:: :fa:`solid fa-microchip` AArch64
+
+      .. code-block:: python
+
+        import lief
+
+        inst: lief.assembly.aarch64.Instruction
+
+        for inst in macho.disassemble(0x400120):
+            print(inst)
+            # Check inst properties
+            if inst.is_branch:
+                print(f"Resolved: {inst.branch_target}")
+
+            for idx, operand in enumerate(inst.operands):
+                if isinstance(operand, lief.assembly.aarch64.operands.Register):
+                    print(f"op[{idx}]: REG - {operand.value}")
+                if isinstance(operand, lief.assembly.aarch64.operands.Memory):
+                    print(f"op[{idx}]: MEM - {operand.base}")
+                if isinstance(operand, lief.assembly.aarch64.operands.PCRelative):
+                    print(f"op[{idx}]: PCR - {operand.value}")
+                if isinstance(operand, lief.assembly.aarch64.operands.Immediate):
+                    print(f"op[{idx}]: IMM - {operand.value}")
+
+   .. tab:: :fa:`solid fa-microchip` x86/x86-64
+
+      .. code-block:: python
+
+        import lief
+
+        inst: lief.assembly.x86.Instruction
+
+        for inst in elf.disassemble(0x1000200):
+            print(inst)
+            # Check inst properties
+            if inst.is_branch:
+                print(f"Resolved: {inst.branch_target}")
+
+            for idx, operand in enumerate(inst.operands):
+                if isinstance(operand, lief.assembly.x86.operands.Register):
+                    print(f"op[{idx}]: REG - {operand.value}")
+                if isinstance(operand, lief.assembly.x86.operands.Memory):
+                    print(f"op[{idx}]: MEM - {operand.base}")
+                if isinstance(operand, lief.assembly.x86.operands.PCRelative):
+                    print(f"op[{idx}]: PCR - {operand.value}")
+                if isinstance(operand, lief.assembly.x86.operands.Immediate):
+                    print(f"op[{idx}]: IMM - {operand.value}")
+
+You can check the documentation of these architectures for more details about
+the exposed API.
+
 Use Cases
 *********
 
@@ -225,6 +281,10 @@ Compared to Capstone, LIEF uses a mainstream LLVM version without any modificati
 on the MC layer. On the other hand, it does not expose a C API, supports fewer
 architectures than Capstone, and does not expose a standalone API.
 
+.. note::
+
+  The current LLVM version is |lief-llvm-version|.
+
 Compared to Nyxstone's disassembler, LLVM is *hidden* from the public API
 which means that LLVM does not need to be installed on the system. On the other
 hand, it does not expose a standalone API.

doc/sphinx/extended/dsc/index.rst

@@ -45,6 +45,11 @@ One can load a shared cache using the |lief-dsc-load| function:
 
         let dyld_cache = lief::dsc::load_from_path("macos-15.0.1/", "");
 
+.. warning::
+
+  |lief-dsc-load| takes as input either a directory for loading the **whole**
+  shared cache or a set of files to load a subset of the cache.
+
 From this |lief-dsc-dyldsharedcache| object, we can inspect the embedded
 |lief-dsc-dylib| as follows:
 
@@ -255,7 +260,7 @@ and configured with:
 
   For all other situations, you should turn on |lief-dsc-enable_cache|.
 
-  **By default, the caching is not enabled.**
+  **By default, the cache mechanism is not enabled.**
 
 .. [1] https://en.cppreference.com/w/cpp/iterator/random_access_iterator