Add support for x86/x86-64 operands

api/python/lief/assembly/__init__.pyi

@@ -1,3 +1,4 @@
+import enum
 from typing import Iterator, Optional, Union
 
 from . import (
@@ -9,12 +10,29 @@ from . import (
     riscv as riscv,
     x86 as x86
 )
+import lief
 
 
 class Engine:
     pass
 
 class Instruction:
+    class MemoryAccess(enum.Flag):
+        @staticmethod
+        def from_value(arg: int, /) -> Instruction.MemoryAccess: ...
+
+        def __eq__(self, arg, /) -> bool: ...
+
+        def __ne__(self, arg, /) -> bool: ...
+
+        def __int__(self) -> int: ...
+
+        NONE = 0
+
+        READ = 1
+
+        WRITE = 2
+
     @property
     def address(self) -> int: ...
 
@@ -41,4 +59,46 @@ class Instruction:
     @property
     def is_syscall(self) -> bool: ...
 
+    @property
+    def is_memory_access(self) -> bool: ...
+
+    @property
+    def is_move_reg(self) -> bool: ...
+
+    @property
+    def is_add(self) -> bool: ...
+
+    @property
+    def is_trap(self) -> bool: ...
+
+    @property
+    def is_barrier(self) -> bool: ...
+
+    @property
+    def is_return(self) -> bool: ...
+
+    @property
+    def is_indirect_branch(self) -> bool: ...
+
+    @property
+    def is_conditional_branch(self) -> bool: ...
+
+    @property
+    def is_unconditional_branch(self) -> bool: ...
+
+    @property
+    def is_compare(self) -> bool: ...
+
+    @property
+    def is_move_immediate(self) -> bool: ...
+
+    @property
+    def is_bitcast(self) -> bool: ...
+
+    @property
+    def memory_access(self) -> Instruction.MemoryAccess: ...
+
+    @property
+    def branch_target(self) -> Union[int, lief.lief_errors]: ...
+
     def __str__(self) -> str: ...