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Daybreak rework #24
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Daybreak rework #24
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… file and #auto_saved_files# (hopefully this does not break anything.
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Today I learned that KiCAD doesn't differentiate between net labels and hierarchical labels if they're named the same thing. Pressing ~ on the net shows that KiCAD thinks they are electrically connected:
consider renaming the name of the nets to be different.
Some ERC stuff:
- the "Foward" pin on the MCU isn't connected to anything (misspelling go brrrr)
- power labels are global so you don't need to have hierarchical labels. Either way, the relevant hierarchical labels aren't on the sheet.
The dashboard PCB has pin 2 of the dashboard connector as BPS hazard and y'all have it as regen.
I thought we were getting rid of the 555 timer in favor of doing it in software? Doing it in hardware is also fine, was just wondering.
Make sure you update all the footprints and ask for a review on that before you start layout.
You shouldn't need to use the "SI8261ABC-IS" gate drivers, you should be able to just use the EL3H7 (right @ppatra126 ?) The gate of the mosfet doesn't sink that much current.
Right_Ind and Left_Ind are at 12V logic and referenced to GNDPWR, so you can't plug it into the gate of your mosfet since the 5V of the timer is referenced to GND (thus breaking the isolation barrier).
…e MinionBrdInterface so that they aren't connected. Changed Regen input to BPS Hazard light since we aren't using regen but will be alerting the driver of BPS faults.
…r to motor can and disconnected shield pins for now since I haven't seen them used (will chack against old version to see what the circuit looked like), copied power-in circuit from contactor board, added optoisolator to timer and blinker light connection.
…pefully this did not involve doing anything that wasn't supposed to be done.
Thank you both for the reviews! Lakshay: We decided we like abstracting the blinky stuff into hardware, so we plan to keep the timer unless @diyarajon prefers software. Prat: Additional changes/concerns:
Thank you very much! |
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I would definitely add a P/N (part number) and footprint to every component on here. Looks like the footprints are OK but double check that they're the ones you want. |
@FrankLiTX @ParthivS20 Our connectors currently all have the clips facing out (like the last Controls leaderboard). Should we flip them to face the inside instead? |
Also for the 12V traces you do have double check to make sure that they can handle the required amount of current. |
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That's probably all of my comments, it's not much but that's just because I'm not used to reviewing PCBs. If a @Lakshay983 or a @Champers5000 or a @FrankLiTX could review this for actual design errors it may be better.
Can you make J1 (the extra ADC connector) a molex connector since the pin headers aren't great for vibration C41 is a bypass cap for the usb-uart chip and it's pretty far away, can you make it closer to the 3v3 pin of that chip Make sure you update your board constraints: https://github.com/lhr-solar/UTSVT-KiCadLibraries?tab=readme-ov-file#standard-constraints-for-laying-out-board since I'm running DRC and it's giving me a ton of nets bridged since your clearance requirement is higher than needed Can you fill some of the areas that aren't filled. It's mostly for ✨ aesthetic ✨ I second Ishan on the 12V trace being a bit odd. I also don't like routing all the current for the lights technically next to the crystal oscillator. Maybe try routing it around the border of the board to get to motor connector. There's also the nuclear option of switching the carcan and motorcan stuff is so you don't need to route the 12V trace as much. The brake pot trace is longer than it needs to be. I think you can move C8 slightly closer to the oscillator and you can fit the trace inside that bus of red traces to go directly into the chip For the 3v3 traces, you can simplify a lil bit since there's some routing on the top and bottom layer going in different directions. you can get rid of this GND trace and via off of pin 47 and C11 by moving the SWDIO via out a little bit so you can form a thermal relief. For pin 63 and 12 instead of a via and long trace you could just do a small trace to a via per pin. I could spin some wacky signal integrity reason like you want both pins to have equal traces to the GND plane but it's mostly for aesthetic and reduction of traces. CAN routing can be improved a little bit so the signal traces aren't branching in a bunch of directions. Why route the break switch through the reset button? Could be routed under the reset button mayhaps. |
Also i don't think you need the 2 CAN testpoints if you have those DB9 outputs, it's also fine to keep em. |
…ctor 2 since we are now using more of the extra GPIO pins; added new components to layout.
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