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metav - Metaprogramming for Verilog

Copyright 2011, 
Kristoffer Ellersgaard Koch <[email protected]>

    This program is free software: you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
    published by the Free Software Foundation, either version 3 of the
    License, or (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see
    <http://www.gnu.org/licenses/>.

--

metav is a tool for extracting information from Verilog files,
processing this information, and generating new Verilog code. All this
within the comfort of expressive python syntax:

module test(input clk, in_a, in_b, output out_a);
  /*metav
  inputs = [i for i in module.get_inputs() if i.name.startswith('in_')]
  output, = [o for o in module.get_outputs()]
  module.append(ast.Assign(output, ast.BinaryOp('^', *inputs))
  */
  /*metav generated:*/
  assign out_a = (in_a ^ in_b);
  /*end metav generated*/

endmodule

metav is written inline in the verilog source code, not unlike
javascript and php (which, although many technical objections, are
hugely successfull). Code emitted is inserted into the file, not
unlike auto-mode for emacs. This avoids confusion that usually occurs
in time-constrained teams, when a second designer comes along and
maybe edits the generated file instead of the generator because:

1) The designer did not realize that this was generated code
2) or.. The generator where nowhere to be found
3) or.. The generator was written in layers upon layers of ugly
        regexes, which the designer did not have the time or will
        to understand

metav might not change this, but at least it's worth a try.

--

metav currently relies on my forked version of ply to work. I hope to
get the required patches upstream, and/or be backwards compatible with
the upstream ply. Please see my ply tree in github for details:
<https://github.com/kristofferkoch/ply>

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Introspective meta programming for Verilog

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