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sunxi: support wk2132 reset gpio.
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to avoid uart does not work in little probability
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@srdgame
srdgame committed Sep 20, 2023
1 parent ef260ec commit 76dc4f3
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Showing 5 changed files with 69 additions and 26 deletions.
2 changes: 1 addition & 1 deletion package/base-files/files/etc/build_version
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
23.09.15
23.09.19
57 changes: 47 additions & 10 deletions target/linux/generic/files/drivers/tty/serial/wk2xxx_spi/wk2xxx_spi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ MODULE_LICENSE("Dual BSD/GPL");
//#define WK_FlowControl_FUNCTION
#define WK_WORK_KTHREAD
//#define WK_RS485_FUNCTION
//#define WK_RSTGPIO_FUNCTION
#define WK_RSTGPIO_FUNCTION
//#define WK_CSGPIO_FUNCTION
/*************SPI control interface******************************/
#define SPI_LEN_LIMIT 30 //MAX<=255
Expand Down Expand Up @@ -321,7 +321,7 @@ static int wk2xxx_read_global_reg(struct spi_device *spi,uint8_t reg,uint8_t *da
int status;
struct spi_transfer index_xfer = {
.len = 2,
// .speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
mutex_lock(&wk2xxxs_reg_lock);
status =0;
Expand Down Expand Up @@ -357,7 +357,7 @@ static int wk2xxx_write_global_reg(struct spi_device *spi,uint8_t reg,uint8_t da
int status;
struct spi_transfer index_xfer = {
.len = 2,
// .speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
mutex_lock(&wk2xxxs_reg_lock);
#ifdef WK_CSGPIO_FUNCTION
Expand Down Expand Up @@ -387,7 +387,7 @@ static int wk2xxx_read_slave_reg(struct spi_device *spi,uint8_t port,uint8_t reg
int status;
struct spi_transfer index_xfer = {
.len = 2,
// .speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
mutex_lock(&wk2xxxs_reg_lock);
#ifdef WK_CSGPIO_FUNCTION
Expand Down Expand Up @@ -424,7 +424,7 @@ static int wk2xxx_write_slave_reg(struct spi_device *spi,uint8_t port,uint8_t re
int status;
struct spi_transfer index_xfer = {
.len = 2,
// .speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
mutex_lock(&wk2xxxs_reg_lock);
#ifdef WK_CSGPIO_FUNCTION
Expand Down Expand Up @@ -457,7 +457,7 @@ static int wk2xxx_read_fifo(struct spi_device *spi,uint8_t port,uint8_t fifolen,
uint8_t transmit_fifo_data[MAX_RFCOUNT_SIZE+1]={0};
struct spi_transfer index_xfer = {
.len = fifolen+1,
//.speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
if(!(fifolen>0)){
printk(KERN_ERR "%s,fifolen error!!\n", __func__);
Expand Down Expand Up @@ -494,7 +494,7 @@ static int wk2xxx_write_fifo(struct spi_device *spi,uint8_t port,uint8_t fifolen
uint8_t transmit_fifo_data[MAX_RFCOUNT_SIZE+1]={0};
struct spi_transfer index_xfer = {
.len = fifolen+1,
// .speed_hz = wk2xxx_spi_speed,
.speed_hz = wk2xxx_spi_speed,
};
if(!(fifolen>0)){
printk(KERN_ERR "%s,fifolen error,fifolen:%d!!\n", __func__,fifolen);
Expand Down Expand Up @@ -907,14 +907,28 @@ static void wk2xxx_start_tx_proc(struct kthread_work *ws)
struct uart_port *port = &(to_wk2xxx_one(ws, start_tx_work)->port);
struct wk2xxx_port *s = dev_get_drvdata(port->dev);

// uint8_t gier,sifr0,sier0,gifr;

uint8_t rx;
#ifdef _DEBUG_WK_FUNCTION
printk(KERN_ALERT "%s!!-port:%ld;--in--\n", __func__,one->port.iobase);
#endif
mutex_lock(&wk2xxxs_lock);

// printk(KERN_ALERT "%s!!-port:%ld spi->mode= 0x%x\n", __func__, one->port.iobase, s->spi_wk->mode);

wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_SIER_REG,&rx);
rx |= WK2XXX_SIER_TFTRIG_IEN_BIT|WK2XXX_SIER_RFTRIG_IEN_BIT|WK2XXX_SIER_RXOUT_IEN_BIT;
wk2xxx_write_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_SIER_REG,rx);

/*
wk2xxx_read_global_reg(s->spi_wk,WK2XXX_GIFR_REG ,&gifr);
wk2xxx_read_global_reg(s->spi_wk,WK2XXX_GIER_REG ,&gier);
wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_SIFR_REG,&sifr0);
wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_SIER_REG,&sier0);
printk(KERN_ALERT "start_tx_proc!!-port:%ld....gifr:%x gier:%x sier:%x sifr:%x \n",one->port.iobase, gifr,gier,sier0,sifr0);
*/

mutex_unlock(&wk2xxxs_lock);
}

Expand Down Expand Up @@ -1297,10 +1311,11 @@ static void conf_wk2xxx_subport(struct uart_port *port)//i
wk2xxx_write_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_BAUD0_REG ,baud0);
wk2xxx_write_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_BAUD1_REG ,baud1);
wk2xxx_write_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_PRES_REG ,pres);
#ifdef _DEBUG_WK_FUNCTION
//#ifdef _DEBUG_WK_FUNCTION
wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_BAUD0_REG,&baud1);
wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_BAUD1_REG,&baud0);
wk2xxx_read_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_PRES_REG,&pres);
#ifdef _DEBUG_WK_FUNCTION
printk(KERN_ALERT "%s!!---baud1:0x%x;baud0:0x%x;pres=0x%X.---\n", __func__,baud1,baud0,pres);
#endif
wk2xxx_write_slave_reg(s->spi_wk,one->port.iobase,WK2XXX_SPAGE_REG ,0);
Expand Down Expand Up @@ -1637,15 +1652,34 @@ static int wk2xxx_probe(struct spi_device *spi)
#ifdef _DEBUG_WK_FUNCTION
printk(KERN_ALERT "%s!!--in--\n", __func__);
#endif

// printk(KERN_ALERT "wk2xxx_probe spi->mode= 0x%x\n", spi->mode);

/* Setup SPI bus */
spi->bits_per_word = 8;
/* only supports mode 0 on WK2124 */
spi->mode = spi->mode ? : SPI_MODE_0;
spi->max_speed_hz = spi->max_speed_hz ? : 10000000;
ret = spi_setup(spi);
if (ret)
return ret;

/* Alloc port structure */
s = devm_kzalloc(&spi->dev, sizeof(*s) +sizeof(struct wk2xxx_one) * NR_PORTS,GFP_KERNEL);
if (!s) {
printk(KERN_ALERT "wk2xxx_probe(devm_kzalloc) fail.\n");
return -ENOMEM;
}
s->spi_wk = spi;
s->devtype=&wk2124_devtype;

if (of_device_is_compatible(spi->dev.of_node, "wkmic,wk2132_spi")) {
printk(KERN_ALERT "wk2xxx_probe as wkmic,wk2132_spi\n");
s->devtype=&wk2132_devtype;
} else {
// Default is wk2124
s->devtype=&wk2124_devtype;
}

dev_set_drvdata(&spi->dev, s);
#ifdef WK_RSTGPIO_FUNCTION
//Obtain the GPIO number of RST signal
Expand Down Expand Up @@ -1687,7 +1721,7 @@ static int wk2xxx_probe(struct spi_device *spi)
/**********************test spi **************************************/

do{
// wk2xxx_read_global_reg(spi,WK2XXX_GENA_REG,dat);
wk2xxx_read_global_reg(spi,WK2XXX_GENA_REG,dat);
wk2xxx_read_global_reg(spi,WK2XXX_GENA_REG,dat);
printk(KERN_ERR "wk2xxx_probe(0x30) GENA = 0x%X\n",dat[0]);//GENA=0X30
wk2xxx_write_global_reg(spi,WK2XXX_GENA_REG,0xf5);
Expand Down Expand Up @@ -1738,6 +1772,7 @@ static int wk2xxx_probe(struct spi_device *spi)
}
}

// FIXME: Should initial the ports as devtype's nr_uart
printk(KERN_ALERT "wk2xxx_serial_init.\n");
for(i =0;i<NR_PORTS;i++){
s->p[i].line = i;
Expand Down Expand Up @@ -1865,6 +1900,8 @@ static int wk2xxx_remove(struct spi_device *spi)
static const struct of_device_id wkmic_spi_dt_match[] = {
//{ .compatible = "wkmic,wk2124_spi", },
{ .compatible = "wkmic,wk2xxx_spi", },
{ .compatible = "wkmic,wk2124_spi" },
{ .compatible = "wkmic,wk2132_spi" },
{ },
};

Expand Down
12 changes: 7 additions & 5 deletions target/linux/sunxi/patches-5.4/910-ARM-dts-sun8i-kooiot-tlink-k1.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
sun8i-s3-olinuxino.dtb \
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-tlink-k1.dts
@@ -0,0 +1,658 @@
@@ -0,0 +1,660 @@
+/*
+ * Copyright (C) 2021 Dirk Chang <[email protected]>
+ *
Expand Down Expand Up @@ -159,11 +159,13 @@
+ gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; /* PB5 */
+ };
+
+ /*
+ wk2xxx_reset_1 {
+ gpio-export,name = "wk2xxx_reset_1";
+ gpio-export,output=<1>;
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 */
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 /
+ };
+ */
+
+ ap_reset {
+ gpio-export,name = "ap_reset";
Expand Down Expand Up @@ -335,17 +337,17 @@
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>; //, <&spi2_reset_pins>;
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>, <&spi2_reset_pins>;
+ status = "okay";
+ wk2xxx_spi: wk2xxx-spi@00 {
+ status = "okay";
+ compatible = "wkmic,wk2xxx_spi";
+ compatible = "wkmic,wk2132_spi";
+ reg = <0x00>;
+ spi-max-frequency = <10000000>;
+ poll_mode = <0>;
+ type = <0>;
+ enable_dma = <0>;
+ // reset_gpio = <&pio 8 9 GPIO_ACTIVE_HIGH>; /* PI9 */
+ reset_gpio = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 */
+ irq_gpio=<&pio 8 15 IRQ_TYPE_LEVEL_LOW>; /* PI15 */
+ };
+};
Expand Down
10 changes: 6 additions & 4 deletions target/linux/sunxi/patches-5.4/914-ARM-dts-sun8i-kooiot-tlink-k2.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
sun8i-s3-olinuxino.dtb \
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-tlink-k2.dts
@@ -0,0 +1,625 @@
@@ -0,0 +1,627 @@
+/*
+ * Copyright (C) 2022 Dirk Chang <[email protected]>
+ *
Expand Down Expand Up @@ -116,11 +116,13 @@
+ gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; /* PB5 */
+ };
+
+ /*
+ wk2xxx_reset_1 {
+ gpio-export,name = "wk2xxx_reset_1";
+ gpio-export,output=<1>;
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 */
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 /
+ };
+ */
+
+ ap_reset {
+ gpio-export,name = "ap_reset";
Expand Down Expand Up @@ -295,7 +297,7 @@
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>; //, <&spi2_reset_pins>;
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>, <&spi2_reset_pins>;
+ status = "okay";
+ wk2xxx_spi: wk2xxx-spi@00 {
+ status = "okay";
Expand All @@ -305,7 +307,7 @@
+ poll_mode = <0>;
+ type = <0>;
+ enable_dma = <0>;
+ // reset_gpio = <&pio 8 9 GPIO_ACTIVE_HIGH>; /* PI9 */
+ reset_gpio = <&pio 8 9 GPIO_ACTIVE_HIGH>; /* PI9 */
+ irq_gpio=<&pio 8 15 IRQ_TYPE_LEVEL_LOW>; /* PI15 */
+ };
+};
Expand Down
14 changes: 8 additions & 6 deletions target/linux/sunxi/patches-5.4/915-ARM-dts-sun8i-kooiot-tlink-k2x.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
sun8i-s3-olinuxino.dtb \
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-tlink-k2x.dts
@@ -0,0 +1,628 @@
@@ -0,0 +1,630 @@
+/*
+ * Copyright (C) 2022 Dirk Chang <[email protected]>
+ *
Expand Down Expand Up @@ -140,11 +140,13 @@
+ gpios = <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */
+ };
+
+ /*
+ ex_uart_reset {
+ gpio-export,name = "ex_uart_reset";
+ gpio-export,output=<1>;
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 */
+ gpios = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 /
+ };
+ */
+
+ can_reset {
+ gpio-export,name = "can_reset";
Expand Down Expand Up @@ -299,22 +301,22 @@
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>; //, <&spi2_reset_pins>;
+ pinctrl-0 = <&spi2_pc_pins>, <&spi2_irq_pins>, <&spi2_reset_pins>;
+ status = "okay";
+
+ spi2_serial: spi2-serial@0 {
+ status = "okay";
+ compatible = "wkmic,wk2xxx_spi";
+ compatible = "wkmic,wk2132_spi";
+ reg = <0x00>;
+ spi-max-frequency = <10000000>;
+ poll_mode = <0>;
+ type = <0>;
+ enable_dma = <0>;
+ // reset_gpio = <&pio 8 9 GPIO_ACTIVE_HIGH>; /* PI9 */
+ reset_gpio = <&pio 8 9 GPIO_ACTIVE_LOW>; /* PI9 */
+ irq_gpio=<&pio 8 15 IRQ_TYPE_LEVEL_LOW>; /* PI15 */
+ };
+
+ mcp2515: mcp2515@0 {
+ mcp2515: mcp2515@1 {
+ compatible = "microchip,mcp2515";
+ reg = <1>;
+ clocks = <&can_clk8m>;
Expand Down

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