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rockchip: update coolsnowwolf patches
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srdgame committed Nov 27, 2024
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Original file line number Diff line number Diff line change
@@ -0,0 +1,73 @@
From 2e1fae80023a38ea03dfca3eab65b3b46617ef3b Mon Sep 17 00:00:00 2001
From: Dragan Simic <[email protected]>
Date: Sun, 30 Jun 2024 18:00:40 +0200
Subject: [PATCH] arm64: dts: rockchip: Add GPU OPP voltage ranges to RK356x
SoC dtsi

Add support for voltage ranges to the GPU OPPs defined in the SoC dtsi for
Rockchip RK356x. This is, for example, useful for RK356x-based boards that
are designed to use the same power supply for the GPU and NPU portions of
the SoC, which is described further in the following documents:

- Rockchip RK3566 Hardware Design Guide, version 1.1.0, page 37
- Rockchip RK3568 Hardware Design Guide, version 1.2, page 78

The values for the exact GPU OPP voltages and the lower limits for the GPU
OPP voltage ranges differ from the values found in the vendor kernel source
(cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support
adjust opp-table by otp")), [1][2] and present the exact GPU OPP voltage
values that have served us well so far.

[1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be7092ab93f564598daa9
[2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi

Suggested-by: Diederik de Haas <[email protected]>
Helped-by: Jonas Karlman <[email protected]>
Signed-off-by: Dragan Simic <[email protected]>
Link: https://lore.kernel.org/r/7e9ba70fd54a21d6f1f267df11e0acabff8d24e0.1719763100.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -154,32 +154,32 @@

opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 1000000>;
};

opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 1000000>;
};

opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 1000000>;
};

opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 1000000>;
};

opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1000000>;
};

opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
};
};

Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
From eb665b1c06bcaf16df10018550d8f467ed4b2887 Mon Sep 17 00:00:00 2001
From: Dragan Simic <[email protected]>
Date: Sun, 30 Jun 2024 18:00:41 +0200
Subject: [PATCH] arm64: dts: rockchip: Update GPU OPP voltages in RK356x SoC
dtsi

Update the values for the exact Rockchip RK356x GPU OPP voltages and the
lower limits for the GPU OPP voltage ranges, using the most conservative
values (i.e. the highest per-OPP voltages) found in the vendor kernel source
(cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support
adjust opp-table by otp")). [1][2]

Using the most conservative per-OPP voltages ensures reliable GPU operation
regardless of the actual GPU binning, with the downside of possibly using
a bit more power than absolutely needed.

[1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be7092ab93f564598daa9
[2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi

Suggested-by: Diederik de Haas <[email protected]>
Helped-by: Jonas Karlman <[email protected]>
Signed-off-by: Dragan Simic <[email protected]>
Link: https://lore.kernel.org/r/80301764e8983c8410c806ed2256403823709897.1719763100.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -154,27 +154,27 @@

opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000 825000 1000000>;
+ opp-microvolt = <850000 850000 1000000>;
};

opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <825000 825000 1000000>;
+ opp-microvolt = <850000 850000 1000000>;
};

opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000 825000 1000000>;
+ opp-microvolt = <850000 850000 1000000>;
};

opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000 825000 1000000>;
+ opp-microvolt = <900000 900000 1000000>;
};

opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <900000 900000 1000000>;
+ opp-microvolt = <950000 950000 1000000>;
};

opp-800000000 {
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
From edcc2833819f6750bf003b95a6ac856aced26274 Mon Sep 17 00:00:00 2001
From: AnYun <[email protected]>
Date: Sat, 18 Mar 2023 23:05:16 +0800
Subject: [PATCH] r8169: add LED configuration from OF

---
drivers/net/ethernet/realtek/r8169_main.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -17,6 +17,7 @@
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
+#include <linux/of.h>
#include <linux/if_vlan.h>
#include <linux/in.h>
#include <linux/io.h>
@@ -173,6 +174,7 @@ enum rtl_registers {
MAR0 = 8, /* Multicast filter. */
CounterAddrLow = 0x10,
CounterAddrHigh = 0x14,
+ CustomLED = 0x18,
TxDescStartAddrLow = 0x20,
TxDescStartAddrHigh = 0x24,
TxHDescStartAddrLow = 0x28,
@@ -5354,6 +5356,22 @@ static bool rtl_aspm_is_safe(struct rtl8
return false;
}

+static int rtl_led_configuration(struct rtl8169_private *tp)
+{
+ u32 led_data;
+ int ret;
+
+ ret = of_property_read_u32(tp->pci_dev->dev.of_node,
+ "realtek,led-data", &led_data);
+
+ if (ret)
+ return ret;
+
+ RTL_W16(tp, CustomLED, led_data);
+
+ return 0;
+}
+
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct rtl8169_private *tp;
@@ -5522,6 +5540,7 @@ static int rtl_init_one(struct pci_dev *
if (!tp->counters)
return -ENOMEM;

+ rtl_led_configuration(tp);
pci_set_drvdata(pdev, tp);

rc = r8169_mdio_register(tp);
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
From edcc2833819f6750bf003b95a6ac856aced26276 Mon Sep 17 00:00:00 2001
From: AnYun <[email protected]>
Date: Mon, 3 Apr 2023 23:26:04 +0800
Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f

---
drivers/net/phy/realtek.c | 9 +++++++++
1 file changed, 9 insertions(+)

--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -28,6 +28,8 @@
#define RTL821x_EXT_PAGE_SELECT 0x1e
#define RTL821x_PAGE_SELECT 0x1f

+#define RTL8211F_LCR 0x10
+#define RTL8211F_EEELCR 0x11
#define RTL8211F_PHYCR1 0x18
#define RTL8211F_PHYCR2 0x19
#define RTL8211F_INSR 0x1d
@@ -382,6 +384,7 @@ static int rtl8211f_config_init(struct p
struct rtl821x_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
u16 val_txdly, val_rxdly;
+ u32 led_data;
int ret;

ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
@@ -448,6 +451,15 @@ static int rtl8211f_config_init(struct p
val_rxdly ? "enabled" : "disabled");
}

+ ret = of_property_read_u32(dev->of_node,
+ "realtek,led-data", &led_data);
+ if (!ret) {
+ phy_write(phydev, RTL821x_PAGE_SELECT, 0xd04);
+ phy_write(phydev, RTL8211F_LCR, led_data);
+ phy_write(phydev, RTL8211F_EEELCR, 0x0);
+ phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
+ }
+
if (priv->has_phycr2) {
ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
RTL8211F_CLKOUT_EN, priv->phycr2);
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <[email protected]>
Date: Wed, 20 Feb 2019 07:38:34 +0000
Subject: [PATCH] mmc: core: set initial signal voltage on power off

Some boards have SD card connectors where the power rail cannot be switched
off by the driver. If the card has not been power cycled, it may still be
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
will fail to boot from a UHS card that continue to use 1.8V signaling.

Set initial signal voltage in mmc_power_off() to allow re-boot to function.

This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
same issue have been seen on some Rockchip RK3399 boards.

I am sending this as a RFC because I have no insights into SD/MMC subsystem,
this change fix a re-boot issue on my boards and does not break emmc/sdio.
Is this an acceptable workaround? Any advice is appreciated.

Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/mmc/core/core.c | 2 ++
1 file changed, 2 insertions(+)

--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host

mmc_pwrseq_power_off(host);

+ mmc_set_initial_signal_voltage(host);
+
host->ios.clock = 0;
host->ios.vdd = 0;

Original file line number Diff line number Diff line change
@@ -0,0 +1,77 @@
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -64,7 +64,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
@@ -87,7 +87,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x1000 0x1000>;
+ msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -117,7 +117,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
@@ -140,7 +140,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x2000 0x1000>;
+ msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -315,14 +315,21 @@

gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
- <0x0 0xfd460000 0 0x80000>; /* GICR */
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd410000>;
- mbi-ranges = <296 24>;
- msi-controller;
+ its: interrupt-controller@fd440000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfd440000 0x0 0x20000>;
+ };
};

usb_host0_ehci: usb@fd800000 {
@@ -990,7 +997,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <2>;
- msi-map = <0x0 &gic 0x0 0x1000>;
+ msi-map = <0x0 &its 0x0 0x1000>;
num-lanes = <1>;
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
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