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This is one of action items in issue daniel5151#29.
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use crate::arch::RegId; | ||
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// TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29) | ||
// pub enum X86RegId {} | ||
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// TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29) | ||
// pub enum X86_64RegId {} | ||
/// 64-bit x86 core + SSE register identifier. | ||
/// | ||
/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml | ||
/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml | ||
#[derive(Debug, Clone, Copy)] | ||
#[non_exhaustive] | ||
pub enum X86_64CoreRegId { | ||
/// General purpose registers: RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, r8-r15 | ||
Gpr(u8), | ||
/// Instruction pointer | ||
Rip, | ||
/// Status register | ||
Eflags, | ||
/// Segment registers: CS, SS, DS, ES, FS, GS | ||
Segment(u8), | ||
/// FPU registers: ST0 through ST7 | ||
St(u8), | ||
/// FPU internal registers: FCTRL, FSTAT, FTAG, FISEG, FIOFF, FOSEG, FOOFF, FOP | ||
Fpu(u8), | ||
/// SIMD Registers: XMM0 through XMM15 | ||
Xmm(u8), | ||
/// SSE Status/Control Register | ||
Mxcsr, | ||
} | ||
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impl RegId for X86_64CoreRegId { | ||
fn from_raw_id(id: usize) -> Option<(Self, usize)> { | ||
use crate::arch::x86::reg::id::X86_64CoreRegId::*; | ||
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let r = match id { | ||
0..=15 => (Gpr(id as u8), 8), | ||
16 => (Rip, 4), | ||
17 => (Eflags, 8), | ||
18..=23 => (Segment(id as u8), 4), | ||
24..=31 => (St(id as u8), 10), | ||
32..=40 => (Fpu(id as u8), 4), | ||
41..=55 => (Xmm(id as u8), 16), | ||
56 => (Mxcsr, 4), | ||
_ => return None, | ||
}; | ||
Some(r) | ||
} | ||
} |