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implement RegId for x86_64
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This is one of action items in issue daniel5151#29.
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keiichiw committed Oct 26, 2020
1 parent da716bd commit 07856eb
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Showing 2 changed files with 48 additions and 8 deletions.
9 changes: 3 additions & 6 deletions src/arch/x86/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,15 +10,12 @@ pub mod reg;
/// Check out the [module level docs](../index.html#whats-with-regidimpl) for
/// more info about the `RegIdImpl` type parameter.
#[allow(non_camel_case_types)]
pub enum X86_64_SSE<RegIdImpl: RegId> {
#[doc(hidden)]
_Marker(core::marker::PhantomData<RegIdImpl>),
}
pub enum X86_64_SSE {}

impl<RegIdImpl: RegId> Arch for X86_64_SSE<RegIdImpl> {
impl Arch for X86_64_SSE {
type Usize = u64;
type Registers = reg::X86_64CoreRegs;
type RegId = RegIdImpl;
type RegId = reg::id::X86_64CoreRegId;

fn target_description_xml() -> Option<&'static str> {
Some(
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47 changes: 45 additions & 2 deletions src/arch/x86/reg/id.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,48 @@
use crate::arch::RegId;

// TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29)
// pub enum X86RegId {}

// TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29)
// pub enum X86_64RegId {}
/// 64-bit x86 core + SSE register identifier.
///
/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml
/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml
#[derive(Debug, Clone, Copy)]
#[non_exhaustive]
pub enum X86_64CoreRegId {
/// General purpose registers: RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, r8-r15
Gpr(u8),
/// Instruction pointer
Rip,
/// Status register
Eflags,
/// Segment registers: CS, SS, DS, ES, FS, GS
Segment(u8),
/// FPU registers: ST0 through ST7
St(u8),
/// FPU internal registers: FCTRL, FSTAT, FTAG, FISEG, FIOFF, FOSEG, FOOFF, FOP
Fpu(u8),
/// SIMD Registers: XMM0 through XMM15
Xmm(u8),
/// SSE Status/Control Register
Mxcsr,
}

impl RegId for X86_64CoreRegId {
fn from_raw_id(id: usize) -> Option<(Self, usize)> {
use crate::arch::x86::reg::id::X86_64CoreRegId::*;

let r = match id {
0..=15 => (Gpr(id as u8), 8),
16 => (Rip, 4),
17 => (Eflags, 8),
18..=23 => (Segment(id as u8), 4),
24..=31 => (St(id as u8), 10),
32..=40 => (Fpu(id as u8), 4),
41..=55 => (Xmm(id as u8), 16),
56 => (Mxcsr, 4),
_ => return None,
};
Some(r)
}
}

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