This is a git repository full of modules used in the CMPE 127 Microprocessor System Design course.
The software is in Verilog and is a Vivado 2017.3 project folder.
None
- From your shell, change your working directory to the intended parent directory.
- Download this repo using
git clone
to your project's intended parent directory, i.e. using the following command:git clone https://github.com/kammce/Motherboard.git
- Please ensure that the dependencies listed above are also added to the parent directory.
You'll need to initialize this project in Xilinx Vivado if:
- You need to edit the file structure of the project to prepare it for pushing upstream
- You need to work directly on the project, proceeding through its RTL design flow
To initialize, open an instance of the Xilinx Vivado GUI, and use [Tools] > [Run Tcl Script...] to run the create_project.tcl
script located in scripts
Note: The Vivado project directory created by create_project.tcl
will bear the same name as the project.
Changes to the project's file structure
- need to be done in Xilinx Vivado, using the [Libraries] tab of [Windows] > [Sources], and
- need to be committed to the
create_project.tcl
usingwriteout_project.tcl
.
Examples of file structure changes include:
- Creating new files/folders
- Renaming files/folders
- Moving files/folders
- Deleting files/folders
Please keep all project files in the Motherboard
folder, such as:
*.xdc
constraint files,*.tcl
script files,*.v
design and simulation sources,*.mem
memory files, and*.wcfg
waveform configuration files.
- Before making your commits, be sure to refer to the previous section, Making modifications, before committing any modifications to the project's file structure.
- Commits and pushes can be done the usual way. Also, be sure your fork and your
git remote
are set up.
- Use your usual
git fetch
andgit merge
routine to update the repo. - Then, be sure to run
create_project.tcl
to rebuild your Vivado project with the changes from upstream.