Remove simulation outfiles

johnjasa · Nov 6, 2019 · 0e31337 · 0e31337
1 parent 91565e3
commit 0e31337
Show file tree

Hide file tree

Showing 6 changed files with 8 additions and 0 deletions.
diff --git a/.gitignore b/.gitignore
@@ -24,10 +24,18 @@ _build
 *.sum
 *.ech
 *.dbg
+*.out
+*.outb
+*.dbg
 
 # Fortran files
 *.85
 
+# Binaries
+*.dylib
+*.so
+*.dll
+
 # Other
 .pytest_cache
 examples/cp_ct_cq_lut.p

diff --git a/Test_Cases/5MW_Baseline/DISCON/DISCON.dll b/Test_Cases/5MW_Baseline/DISCON/DISCON.dll
diff --git a/Test_Cases/5MW_Baseline/DISCON/DISCON_OC3Hywind.dll b/Test_Cases/5MW_Baseline/DISCON/DISCON_OC3Hywind.dll
diff --git a/Test_Cases/5MW_Baseline/DISCON/DISCON_glin64.so b/Test_Cases/5MW_Baseline/DISCON/DISCON_glin64.so
diff --git a/examples/test_controller/DISCON.dll b/examples/test_controller/DISCON.dll
diff --git a/examples/test_controller/DISCON_glin64.so b/examples/test_controller/DISCON_glin64.so