Lab3 #12
Lab3 #12
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ghost
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I have quite a few comments on style. It might seem silly, but we need to lead by example and show the students how to write high quality code. We must follow style guidelines.
Otherwise, most of the changes seem fine to me. If you can go through my comments and either make the changes or respond the the comment by Friday evening, I'd appreciate it. I'll spend some time Saturday or Sunday working on writing up the rest of the lab.
| val forwardA = Output(UInt(2.W)) | ||
| val forwardB = Output(UInt(2.W)) | ||
| }) | ||
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| //printf("rs1 = %d, rs2 =%d, exmemrd = %d, exmemrw = %d,memwbrd = %d, memwbrw = %x,forwardA = %d, forwardB =%d ",io.rs1,io.rs2,io.exmemrd,io.exmemrw,io.memwbrd,io.memwbrw,io.forwardA,io.forwardB) |
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Don't leave things commented out. Either delete the line, uncomment the line, or add a flag to enable it at runtime.
| when (io.rs1 === io.exmemrd && io.exmemrd =/= 0.U && io.exmemrw) { | ||
| io.forwardA := 1.U | ||
| } .elsewhen (io.rs1 === io.memwbrd && io.memwbrd =/= 0.U && io.memwbrw) { | ||
| } .elsewhen (io.rs1 === io.memwbrd && io.memwbrd =/= 0.U && io.memwbrw && ~(io.exmemrw && io.exmemrd =/=0.U && io.exmemrd ===io.rs1)) { |
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This doesn't make sense to me. Isn't it the same as in the when clause?
| io.forwardA := 2.U | ||
| } .otherwise { | ||
| } |
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How does this compile? Isn't this an extra }
| io.forwardA := 0.U | ||
| } | ||
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| when (io.rs2 === io.exmemrd && io.exmemrd =/= 0.U && io.exmemrw) { | ||
| io.forwardB := 1.U | ||
| } .elsewhen (io.rs2 === io.memwbrd && io.memwbrd =/= 0.U && io.memwbrw) { | ||
| } .elsewhen (io.rs2 === io.memwbrd && io.memwbrd =/= 0.U && io.memwbrw&& ~(io.exmemrw && io.exmemrd =/=0.U && io.exmemrd ===io.rs2)) { |
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Ditto above. This shouldn't be needed, unless I'm missing something.
| io.forwardB := 2.U | ||
| } .otherwise { | ||
| }.otherwise { |
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Revert this line. Why did you get rid of this space?
| @@ -39,6 +40,7 @@ addi a5,a5,1 | |||
| sw a5,0x500(zero) | |||
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| label2: | |||
| nop | |||
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| val forward_inputx = Wire(UInt(32.W)) |
src/main/scala/pipelined/cpu.scala
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| ex_mem.mcontrol.jump := id_ex.mcontrol.jump | ||
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| printf("branch control taken = %d\n", branchCtrl.io.taken) | ||
| printf("jump = %d\n", id_ex.mcontrol.jump) |
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Are these prints necessary?
src/main/scala/pipelined/cpu.scala
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| @@ -253,8 +339,9 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends Module { | |||
| (mem_wb.wbcontrol.toreg === 0.U) -> mem_wb.aluresult, | |||
| (mem_wb.wbcontrol.toreg === 1.U) -> mem_wb.readdata, | |||
| (mem_wb.wbcontrol.toreg === 2.U) -> mem_wb.pcplusfour)) | |||
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| printf("write_data = %d\n", write_data) | |||
src/test/resources/risc-v/lw1.riscv
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| _last: | ||
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| .data | ||
| .byte 0xFF,0xFF,0xFF,0xFF | ||
| .word 4294967295 |
Signed-off-by: Jason Lowe-Power <[email protected]>
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@FilipeEduardo, I just tried to build/run the tests, but I'm receiving a ton of errors. It looks like there's a cycle in the combinational logic. Thanks! |
I ran all the tests again to see which ones fail. The only tests that fail are the multicycle instructions for the five-cycle CPU. All tests pass for the Pipelined CPU. |
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I think you forgot to commit something. I'm seeing "Tests: succeeded 3, failed 68, canceled 0, ignored 0, pending 0" |
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Nevermind. when I run "Lab3 / test" it works, but when I run "test" it doesn't. What tests broke? |
Signed-off-by: Jason Lowe-Power <[email protected]>
Signed-off-by: Jason Lowe-Power <[email protected]>
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I fixed the register file, btw. I used a scala if to check if we were running the single cycle or the pipelined/five-cycle versions. I'm going to close this PR and delete this branch so I can use the branch name for something else. Thanks! |
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