Move CoreIO into base cpu file

src/main/scala/base-cpu.scala

@@ -6,11 +6,17 @@ import chisel3._
 /**
   * Base CPU module which all CPU models implement
   */
-abstract class BaseCPU extends Module {
+
+class CoreIO extends Bundle {
+  val imem = Flipped(new IMemPortIO)
+  val dmem = Flipped(new DMemPortIO)
+}
+
+class BaseCPU extends Module {
   val io = IO(new CoreIO())
 
   // These signals are not and should not be used in the CPU implementation at all -
   // they correspond with the port<=>memory connection, but we are in the pipeline<=> port side
-  io.imem.bus <> DontCare
-  io.dmem.bus <> DontCare
+  io.imem.bus <> 0.U.asTypeOf(new MemPortBusIO)
+  io.dmem.bus <> 0.U.asTypeOf(new MemPortBusIO)
 }