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Remove IAR patches from ARMmbed#14900
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@jeromecoutant
jeromecoutant committed Aug 23, 2021
1 parent 3377f08 commit 5c0ca65
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Showing 7 changed files with 361 additions and 511 deletions.
21 changes: 10 additions & 11 deletions cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -18,13 +18,12 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv7-A Exception handlers
; * Title: Cortex-A Exception handlers
; *
; * -----------------------------------------------------------------------------
; */

NAME irq_armv7a.s

NAME irq_ca.s

MODE_FIQ EQU 0x11
MODE_IRQ EQU 0x12
Expand Down Expand Up @@ -353,16 +352,16 @@ osRtxContextSave
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment

VSTMDB R1!, {D0-D15} ; Save D0-D15
#ifdef __ARM_ADVANCED_SIMD__
#ifdef __ARM_ADVANCED_SIMD__
VSTMDB R1!, {D16-D31} ; Save D16-D31
#endif
#endif

LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
#ifdef __ARM_ADVANCED_SIMD__
#ifdef __ARM_ADVANCED_SIMD__
ORR R2, R2, #4 ; NEON state
#else
#else
ORR R2, R2, #2 ; VFP state
#endif
#endif
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state

osRtxContextSave1
Expand Down Expand Up @@ -414,9 +413,9 @@ osRtxContextRestore
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
#ifdef __ARM_ADVANCED_SIMD__
#ifdef __ARM_ADVANCED_SIMD__
VLDMIA LR!, {D16-D31} ; Restore D16-D31
#endif
#endif
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
Expand Down
57 changes: 14 additions & 43 deletions cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -18,23 +18,18 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv6-M Exception handlers
; * Title: Cortex-M0 Exception handlers
; *
; * -----------------------------------------------------------------------------
; */


NAME irq_armv6m.s
NAME irq_cm0.s


#include "rtx_def.h"

I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset

osRtxErrorStackOverflow\
EQU 1 ; Stack overflow


PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
Expand All @@ -52,10 +47,6 @@ SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif

MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
Expand All @@ -66,7 +57,7 @@ SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0 ; Check SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0

PUSH {R0,LR} ; Save SP and EXC_RETURN
Expand All @@ -77,49 +68,29 @@ SVC_Number
MOV LR,R3 ; Set EXC_RETURN

SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same

SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
CMP R1,#0
BEQ SVC_ContextRestore ; Branch if running thread is deleted
BEQ SVC_ContextSwitch ; Branch if running thread is deleted

SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
SUBS R0,R0,#32 ; Calculate SP
STR R0,[R1,#TCB_SP_OFS] ; Store SP

#ifdef RTX_STACK_CHECK

PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CMP R0,#0
BNE SVC_ContextSaveRegs ; Branch when stack check is ok

MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
B SVC_ContextRestore ; Branch to context restore handling

SVC_ContextSaveRegs
LDR R0,[R1,#TCB_SP_OFS] ; Load SP

#endif

STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11

SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next

SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
Expand All @@ -132,7 +103,7 @@ SVC_ContextRestore
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7

MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MOVS R0,#~0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler

Expand Down Expand Up @@ -170,7 +141,7 @@ PendSV_Handler
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
B SVC_Context


SysTick_Handler
Expand All @@ -181,7 +152,7 @@ SysTick_Handler
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
B SVC_Context


END
57 changes: 14 additions & 43 deletions cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -18,23 +18,18 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv6-M Exception handlers
; * Title: Cortex-M0 Exception handlers
; *
; * -----------------------------------------------------------------------------
; */


NAME irq_armv6m.s
NAME irq_cm0.s


#include "rtx_def.h"

I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset

osRtxErrorStackOverflow\
EQU 1 ; Stack overflow


PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
Expand All @@ -52,10 +47,6 @@ SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif

MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
Expand All @@ -66,7 +57,7 @@ SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0 ; Check SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0

PUSH {R0,LR} ; Save SP and EXC_RETURN
Expand All @@ -77,49 +68,29 @@ SVC_Number
MOV LR,R3 ; Set EXC_RETURN

SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same

SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
CMP R1,#0
BEQ SVC_ContextRestore ; Branch if running thread is deleted
BEQ SVC_ContextSwitch ; Branch if running thread is deleted

SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
SUBS R0,R0,#32 ; Calculate SP
STR R0,[R1,#TCB_SP_OFS] ; Store SP

#ifdef RTX_STACK_CHECK

PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CMP R0,#0
BNE SVC_ContextSaveRegs ; Branch when stack check is ok

MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
B SVC_ContextRestore ; Branch to context restore handling

SVC_ContextSaveRegs
LDR R0,[R1,#TCB_SP_OFS] ; Load SP

#endif

STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11

SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next

SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
Expand All @@ -132,7 +103,7 @@ SVC_ContextRestore
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7

MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MOVS R0,#~0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler

Expand Down Expand Up @@ -170,7 +141,7 @@ PendSV_Handler
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
B SVC_Context


SysTick_Handler
Expand All @@ -181,7 +152,7 @@ SysTick_Handler
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
B SVC_Context


END
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