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[dv/adc_ctrl] Add some condition coverage UNR to reach V2
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This PR adds some condition coverage CDC reg UNR to reach V2 coverage
goal. This UNR should be removed and re-reviewed upon reaching V3.

Signed-off-by: Cindy Chen <[email protected]>
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@cindychip @jeoongp
cindychip authored and jeoongp committed May 6, 2022
1 parent cfa48ad commit f898a62
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3 changes: 3 additions & 0 deletions hw/ip/adc_ctrl/dv/adc_ctrl_sim_cfg.hjson
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// Default iterations for all tests - each test entry can override this.
reseed: 50

// Add ADC_CTRL specific exclusion files.
vcs_cov_excl_files: ["{proj_root}/hw/ip/adc_ctrl/dv/cov/adc_ctrl_cov_unr_excl.el"]

// Default UVM test and seq class name.
uvm_test: adc_ctrl_base_test
uvm_test_seq: adc_ctrl_base_vseq
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99 changes: 99 additions & 0 deletions hw/ip/adc_ctrl/dv/cov/adc_ctrl_cov_unr_excl.el
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Manually selected condition coverage UNR items from auto-generated UNR file to help reach V2
// coverage metrics.
//==================================================
// This file contains the Excluded objects
// Generated By User: chencindy
// Format Version: 2
// Date: Thu Apr 21 15:18:07 2022
// ExclMode: default
//==================================================
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_en_ctl_cdc
ANNOTATION: "[UNR]: busy is always 1 when src_req is high."
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_pd_ctl_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_sample_ctl_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_fsm_rst_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn_val_0_cdc
Condition 3 "4189518658" "((src_busy_q && src_ack) || (src_update_i && ((!busy)))) 1 -1" (3 "10")
Condition 1 "1013867581" "(src_busy_q && src_ack) 1 -1" (2 "10")
Condition 1 "1013867581" "(src_busy_q && src_ack) 1 -1" (3 "11")
Condition 4 "4258753323" "(src_busy_q && src_ack) 1 -1" (2 "10")
Condition 4 "4258753323" "(src_busy_q && src_ack) 1 -1" (3 "11")
Condition 5 "1421151491" "(src_update_i && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_chn_val_1_cdc
Condition 3 "4189518658" "((src_busy_q && src_ack) || (src_update_i && ((!busy)))) 1 -1" (3 "10")
Condition 4 "4258753323" "(src_busy_q && src_ack) 1 -1" (2 "10")
Condition 4 "4258753323" "(src_busy_q && src_ack) 1 -1" (3 "11")
Condition 5 "1421151491" "(src_update_i && ((!busy))) 1 -1" (2 "10")
Condition 1 "1013867581" "(src_busy_q && src_ack) 1 -1" (2 "10")
Condition 1 "1013867581" "(src_busy_q && src_ack) 1 -1" (3 "11")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_adc_wakeup_ctl_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")
CHECKSUM: "2208754432 2034735209"
INSTANCE: tb.dut.u_reg.u_filter_status_cdc
Condition 2 "2823382532" "(src_req && ((!busy))) 1 -1" (2 "10")

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