added memtop to machine definition and asm source code check

added %memtop directive
irmen · Nov 1, 2024 · 3b79809 · 3b79809
1 parent 6fb05bd
commit 3b79809
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Showing 31 changed files with 92 additions and 45 deletions.
diff --git a/codeCore/src/prog8/code/core/CompilationOptions.kt b/codeCore/src/prog8/code/core/CompilationOptions.kt
@@ -14,6 +14,7 @@ class CompilationOptions(val output: OutputType,
                          val compTarget: ICompilationTarget,
                          // these are set later, based on command line arguments or options in the source code:
                          var loadAddress: UInt,
+                         var memtopAddress: UInt,
                          var warnSymbolShadowing: Boolean = false,
                          var optimize: Boolean = false,
                          var asmQuiet: Boolean = false,

diff --git a/codeCore/src/prog8/code/core/IMachineDefinition.kt b/codeCore/src/prog8/code/core/IMachineDefinition.kt
@@ -14,6 +14,7 @@ interface IMachineDefinition {
     val FLOAT_MAX_POSITIVE: Double
     val FLOAT_MEM_SIZE: Int
     val PROGRAM_LOAD_ADDRESS : UInt
+    val PROGRAM_TOP_ADDRESS: UInt
     val BSSHIGHRAM_START: UInt
     val BSSHIGHRAM_END: UInt
     val BSSGOLDENRAM_START: UInt

diff --git a/codeCore/src/prog8/code/target/atari/AtariMachineDefinition.kt b/codeCore/src/prog8/code/target/atari/AtariMachineDefinition.kt
@@ -12,6 +12,7 @@ class AtariMachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = -9.999999999e97
     override val FLOAT_MEM_SIZE = 6
     override val PROGRAM_LOAD_ADDRESS = 0x2000u
+    override val PROGRAM_TOP_ADDRESS = 0xffffu  // TODO what's memtop
 
     override val BSSHIGHRAM_START = 0u    // TODO
     override val BSSHIGHRAM_END = 0u      // TODO

diff --git a/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt b/codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt
@@ -14,6 +14,7 @@ class C128MachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
     override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
     override val PROGRAM_LOAD_ADDRESS = 0x1c01u
+    override val PROGRAM_TOP_ADDRESS = 0xfeffu
 
     override val BSSHIGHRAM_START = 0u    // TODO
     override val BSSHIGHRAM_END = 0u      // TODO

diff --git a/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt b/codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt
@@ -15,6 +15,7 @@ class C64MachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
     override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
     override val PROGRAM_LOAD_ADDRESS = 0x0801u
+    override val PROGRAM_TOP_ADDRESS = 0xbfffu
 
     override val BSSHIGHRAM_START = 0xc000u
     override val BSSHIGHRAM_END = 0xcfffu

diff --git a/codeCore/src/prog8/code/target/cx16/CX16MachineDefinition.kt b/codeCore/src/prog8/code/target/cx16/CX16MachineDefinition.kt
@@ -14,6 +14,7 @@ class CX16MachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
     override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
     override val PROGRAM_LOAD_ADDRESS = 0x0801u
+    override val PROGRAM_TOP_ADDRESS = 0x9effu
 
     override val BSSHIGHRAM_START = 0xa000u     // hiram bank 1, 8Kb, assumed to be active
     override val BSSHIGHRAM_END = 0xbfffu       // Rom starts at $c000

diff --git a/codeCore/src/prog8/code/target/pet/PETMachineDefinition.kt b/codeCore/src/prog8/code/target/pet/PETMachineDefinition.kt
@@ -14,6 +14,7 @@ class PETMachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
     override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
     override val PROGRAM_LOAD_ADDRESS = 0x0401u
+    override val PROGRAM_TOP_ADDRESS = 0x7fffu
 
     override val BSSHIGHRAM_START = 0u
     override val BSSHIGHRAM_END = 0u

diff --git a/codeCore/src/prog8/code/target/virtual/VirtualMachineDefinition.kt b/codeCore/src/prog8/code/target/virtual/VirtualMachineDefinition.kt
@@ -14,6 +14,7 @@ class VirtualMachineDefinition: IMachineDefinition {
     override val FLOAT_MAX_NEGATIVE = -Float.MAX_VALUE.toDouble()
     override val FLOAT_MEM_SIZE = 8             // 64-bits double
     override val PROGRAM_LOAD_ADDRESS = 0u      // not actually used
+    override val PROGRAM_TOP_ADDRESS = 0xffffu  // not actually used
 
     override val BSSHIGHRAM_START = 0u          // not actually used
     override val BSSHIGHRAM_END = 0u            // not actually used

diff --git a/codeGenCpu6502/src/prog8/codegen/cpu6502/ProgramAndVarsGen.kt b/codeGenCpu6502/src/prog8/codegen/cpu6502/ProgramAndVarsGen.kt
@@ -284,6 +284,8 @@ internal class ProgramAndVarsGen(
                 asmgen.out("  .cerror * > ${relocatedBssEnd.toHex()}, \"too many data for slabs_BSS section\"")
             }
         }
+        asmgen.out("  ; memtop check")
+        asmgen.out("  .cerror * > ${options.memtopAddress.toHex()}, \"Program too long by \", * - ${options.memtopAddress.toHex()}, \" bytes, memtop=${options.memtopAddress.toHex()}\"")
     }
 
     private fun block2asm(block: PtBlock) {

diff --git a/codeGenCpu6502/test/TestCodegen.kt b/codeGenCpu6502/test/TestCodegen.kt
@@ -26,7 +26,8 @@ class TestCodegen: FunSpec({
             floats = true,
             noSysInit = false,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS
+            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            memtopAddress = 0xffffu
         )
     }
 

diff --git a/codeGenIntermediate/test/TestIRPeepholeOpt.kt b/codeGenIntermediate/test/TestIRPeepholeOpt.kt
@@ -22,7 +22,8 @@ class TestIRPeepholeOpt: FunSpec({
             floats = false,
             noSysInit = true,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS
+            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            memtopAddress = 0xffffu
         )
         val prog = IRProgram("test", IRSymbolTable(), options, target)
         prog.addBlock(block)

diff --git a/codeGenIntermediate/test/TestVmCodeGen.kt b/codeGenIntermediate/test/TestVmCodeGen.kt
@@ -23,7 +23,8 @@ class TestVmCodeGen: FunSpec({
             floats = true,
             noSysInit = false,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS
+            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            memtopAddress = 0xffffu
         )
     }
 

diff --git a/compiler/src/prog8/compiler/Compiler.kt b/compiler/src/prog8/compiler/Compiler.kt
@@ -263,6 +263,7 @@ internal fun determineProgramLoadAddress(program: Program, options: CompilationO
     }
 
     options.loadAddress = loadAddress
+    options.memtopAddress = program.toplevelModule.memtopAddress?.first ?: options.compTarget.machine.PROGRAM_TOP_ADDRESS
 }
 
 
@@ -398,7 +399,7 @@ fun determineCompilationOptions(program: Program, compTarget: ICompilationTarget
     return CompilationOptions(
         outputType, launcherType,
         zpType, zpReserved, zpAllowed, floatsEnabled, noSysInit,
-        compTarget, 0u
+        compTarget, 0u, 0xffffu
     )
 }
 

diff --git a/compiler/src/prog8/compiler/ModuleImporter.kt b/compiler/src/prog8/compiler/ModuleImporter.kt
@@ -110,7 +110,7 @@ class ModuleImporter(private val program: Program,
 
     private fun removeDirectivesFromImportedModule(importedModule: Module) {
         // Most global directives don't apply for imported modules, so remove them
-        val moduleLevelDirectives = listOf("%output", "%launcher", "%zeropage", "%zpreserved", "%zpallowed", "%address")
+        val moduleLevelDirectives = listOf("%output", "%launcher", "%zeropage", "%zpreserved", "%zpallowed", "%address", "%memtop")
         var directives = importedModule.statements.filterIsInstance<Directive>()
         importedModule.statements.removeAll(directives.toSet())
         directives = directives.filter{ it.directive !in moduleLevelDirectives }

diff --git a/compiler/src/prog8/compiler/astprocessing/AstChecker.kt b/compiler/src/prog8/compiler/astprocessing/AstChecker.kt
@@ -57,7 +57,7 @@ internal class AstChecker(private val program: Program,
         val directives = module.statements.filterIsInstance<Directive>().groupBy { it.directive }
         directives.filter { it.value.size > 1 }.forEach{ entry ->
             when(entry.key) {
-                "%output", "%launcher", "%zeropage", "%address", "%encoding" ->
+                "%output", "%launcher", "%zeropage", "%address", "%memtop", "%encoding" ->
                     entry.value.forEach { errors.err("directive can just occur once", it.position) }
             }
         }
@@ -962,6 +962,12 @@ internal class AstChecker(private val program: Program,
                 if(directive.args.size!=1 || directive.args[0].int == null)
                     err("invalid address directive, expected numeric address argument")
             }
+            "%memtop" -> {
+                if(directive.parent !is Module)
+                    err("this directive may only occur at module level")
+                if(directive.args.size!=1 || directive.args[0].int == null)
+                    err("invalid memtop directive, expected numeric address argument")
+            }
             "%import" -> {
                 if(directive.parent !is Module)
                     err("this directive may only occur at module level")

diff --git a/compiler/src/prog8/compiler/astprocessing/StatementReorderer.kt b/compiler/src/prog8/compiler/astprocessing/StatementReorderer.kt
@@ -22,7 +22,7 @@ internal class StatementReorderer(
     // - sorts the choices in when statement.
     // - insert AddressOf (&) expression where required (string params to a UWORD function param etc.).
 
-    private val directivesToMove = setOf("%output", "%launcher", "%zeropage", "%zpreserved", "%zpallowed", "%address", "%option", "%encoding")
+    private val directivesToMove = setOf("%output", "%launcher", "%zeropage", "%zpreserved", "%zpallowed", "%address", "%memtop", "%option", "%encoding")
 
     override fun after(module: Module, parent: Node): Iterable<IAstModification> {
         val (blocks, other) = module.statements.partition { it is Block }

diff --git a/compiler/test/TestGoldenRam.kt b/compiler/test/TestGoldenRam.kt
@@ -20,7 +20,8 @@ class TestGoldenRam: FunSpec({
         floats = true,
         noSysInit = false,
         compTarget = VMTarget(),
-        loadAddress = 999u
+        loadAddress = 999u,
+        memtopAddress = 0xffffu
     )
 
     test("empty golden ram allocations") {