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Example_CORDIC/Verilog Design/Verilog Codes/CORDIC.v

@@ -0,0 +1,170 @@
+/***********************************************
+Module Name:   CORDIC
+Feature:       CORDIC algorithm
+               An example for the GEM Projects
+Coder:         Garfield
+Organization:  xxxx Group, Department of Architecture
+------------------------------------------------------
+Input ports:   clk: System clock
+               Reset_n: System reset
+               opernd: input number to be calculated
+Output Ports:  results: results of operation
+------------------------------------------------------
+History:
+06-21-2016: First Version by Garfield
+06-21-2016: Verified by CORDIC_Test
+***********************************************/
+`define ORDER 12
+// CORDIC order by simulation
+`define WIDTH 15
+//CORDIC ports bit width by simulatation
+`define K 14'h26DD
+
+module CORDIC
+#(parameter MODE = 1)
+//CORDIC Mode
+   ( 
+    CLK,
+    RESET_n,
+    operand,
+    results
+   );
+localparam PORT_WIDTH = (MODE == 3) ? (7 + `WIDTH) : ( (MODE == 2) ? (2 + `WIDTH) :(`WIDTH));
+localparam IN_WIDTH = 2 * PORT_WIDTH;
+localparam OUT_WIDTH = 2 * PORT_WIDTH;
+localparam ONE = 15'd16384;
+
+input CLK;
+input RESET_n;
+input signed[(IN_WIDTH - 1) : 0] operand;
+output signed[(OUT_WIDTH - 1) : 0] results;
+
+wire[(PORT_WIDTH-1):0] x[(`ORDER+1):0];
+wire[(PORT_WIDTH-1):0] y[(`ORDER+1):0];
+wire[(PORT_WIDTH-1):0] z[(`ORDER+1):0];
+//middle signals
+
+generate
+begin
+	case(MODE)
+		1:
+		begin
+			assign x[0] = `K;
+			assign y[0] = 14'h0;
+			assign z[0] = operand[PORT_WIDTH -1 : 0];
+		end
+		2:
+		begin
+			assign x[0] = ONE;
+			assign y[0] = operand[PORT_WIDTH -1 : 0];
+			assign z[0] = 14'h0;
+		end
+		3:
+		begin
+			assign x[0] = operand[PORT_WIDTH -1 : 0];
+			assign y[0] = operand[2*PORT_WIDTH  -1 : PORT_WIDTH];
+			assign z[0] = 14'h0;
+		end
+		default:
+		begin
+			assign x[0] = `K;
+			assign y[0] = 14'h0;
+			assign z[0] = operand[PORT_WIDTH -1 : 0];
+		end
+	endcase
+end
+endgenerate
+
+generate
+begin
+	case(MODE)
+		1:
+		begin
+			assign results = {x[13], y[13]};
+		end
+		2:
+		begin
+			assign results = {{(PORT_WIDTH){1'b0}}, z[13]};
+		end
+		3:
+		begin
+			assign results = {{(PORT_WIDTH){1'b0}}, x[13]};
+		end
+		default:
+		begin
+			assign results = {x[13], y[13]};
+		end
+	endcase
+end
+endgenerate		
+
+//CORDIC pipeline
+//Connection to the modules
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h3243), .ORDER(0), .MODE(MODE) )
+   CE0   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[0]), .y_k(y[0]), .z_k(z[0]), 
+           .x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h1DAC), .ORDER(1), .MODE(MODE)  )
+   CE1   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[1]), .y_k(y[1]), .z_k(z[1]), 
+           .x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2])  );           
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0FAD), .ORDER(2), .MODE(MODE)  )
+   CE2   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[2]), .y_k(y[2]), .z_k(z[2]), 
+           .x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h07F5), .ORDER(3) , .MODE(MODE) )
+   CE3   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[3]), .y_k(y[3]), .z_k(z[3]), 
+           .x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h03FE), .ORDER(4) , .MODE(MODE) )
+   CE4   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[4]), .y_k(y[4]), .z_k(z[4]), 
+           .x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h01FF), .ORDER(5) , .MODE(MODE) )
+   CE5   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[5]), .y_k(y[5]), .z_k(z[5]), 
+           .x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6])  );
+
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h00FF), .ORDER(6) , .MODE(MODE) )
+   CE6   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[6]), .y_k(y[6]), .z_k(z[6]), 
+           .x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7])  );
+
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h007F), .ORDER(7) , .MODE(MODE) )
+   CE7   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[7]), .y_k(y[7]), .z_k(z[7]), 
+           .x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h003F), .ORDER(8) , .MODE(MODE) )
+   CE8   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[8]), .y_k(y[8]), .z_k(z[8]), 
+           .x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9])  ); 
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h001F), .ORDER(9) , .MODE(MODE) )
+   CE9   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[9]), .y_k(y[9]), .z_k(z[9]), 
+           .x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h000F), .ORDER(10) , .MODE(MODE) )
+   CE10   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[10]), .y_k(y[10]), .z_k(z[10]), 
+           .x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0007), .ORDER(11) , .MODE(MODE) )
+   CE11   ( .CLK(CLK), .RESET_n(RESET_n),
+           .x_k(x[11]), .y_k(y[11]), .z_k(z[11]), 
+           .x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12])  );
+
+CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0003), .ORDER(12) , .MODE(MODE) )
+   CE12   ( .CLK(CLK), .RESET_n(RESET_n), 
+           .x_k(x[12]), .y_k(y[12]), .z_k(z[12]), 
+           .x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13])  );
+
+endmodule

Example_CORDIC/Verilog Design/Verilog Codes/CORDIC_Element.v

@@ -22,7 +22,8 @@ parameter VALUE_WIDTH = 8,
 //Output value's bit width, internal one, for x_k and y_k
 parameter[ADDRESS_WIDTH - 1 : 0] e_k = 2**(ADDRESS_WIDTH - 1),
 //The rotation angle in this step
-parameter ORDER = 0)
+parameter ORDER = 0,
+parameter MODE = 1)
 //Order of this element
 
 
@@ -41,14 +42,25 @@ parameter ORDER = 0)
 wire d_k;
 
 //Logicals
-assign d_k = z_k[ADDRESS_WIDTH];
-//Get the symbol of z_k
+generate
+  if (MODE == 1)
+    begin
+        assign d_k = z_k[ADDRESS_WIDTH];
+        //Get the symbol of z_k
+    end
+  else
+    begin
+        assign d_k = ~(x_k[ADDRESS_WIDTH]^y_k[ADDRESS_WIDTH]);
+        //Get the symbol of -x_k * y_k
+    end
+endgenerate
+
 
 //z_k calculation
 //Angle rotation operation
-always @ (posedge CLK or negedge RESET)
+always @ (posedge CLK or negedge RESET_n)
 begin
-    if (!RESET)
+    if (!RESET_n)
     begin
         z_k1 <= {(ADDRESS_WIDTH){1'b0}};
     end
@@ -66,9 +78,9 @@ end
 
 //x_k and z_k calculation
 //Value operation
-always @ (posedge CLK or negedge RESET)
+always @ (posedge CLK or negedge RESET_n)
 begin
-    if (!RESET)
+    if (!RESET_n)
     begin
         x_k1 <= {(VALUE_WIDTH){1'b0}};
     end
@@ -84,9 +96,9 @@ begin
     end
 end
 
-always @ (posedge CLK or negedge RESET)
+always @ (posedge CLK or negedge RESET_n)
 begin
-    if (!RESET)
+    if (!RESET_n)
     begin
         y_k1 <= {(VALUE_WIDTH){1'b0}};
     end
@@ -101,4 +113,4 @@ begin
         y_k1 <= y_k - (x_k>>>ORDER);
     end
 end
-endmodule
+endmodule

Example_CORDIC/Verilog Design/Verilog Codes/CORDIC_Element_test.v

@@ -12,7 +12,7 @@ Variables:
          
 ------------------------------------------------------
 History:
-12-20-2015: First Version by Garfield
+06-20-2016: First Version by Garfield
 ***********************************************/
 `timescale 10 ns/100 ps
 //Simulation time assignment
@@ -143,9 +143,13 @@ CORDIC_elemet #(.ADDRESS_WIDTH(`WIDTH-1), .VALUE_WIDTH(`WIDTH-1), .e_k(14'h0003)
     end
 
 //Load the input of 0 order element
+//assign      x[0] = test_vector_x[0];
+//assign      y[0] = test_vector_y[0];
+//assign      z[0] = test_vector_z[0];
+
 assign      x[0] = test_vector_x[0];
 assign      y[0] = test_vector_y[0];
-assign      z[0] = test_vector_z[0];
+assign      z[0] = 0;
 
 //Comparision
     always @(posedge clk)
@@ -164,11 +168,11 @@ assign      z[0] = test_vector_z[0];
         begin
             for (loop = 0; loop <= (`ORDER+1); loop = loop + 1)
             begin
-                comp_x[loop] <= (x[loop] - test_vector_x[loop]);
-                comp_y[loop] <= (y[loop] - test_vector_y[loop]);
-                comp_z[loop] <= (z[loop] - test_vector_z[loop]);
+                comp_x[loop] <= (x[loop]>>>1 - test_vector_x[loop]);
+                comp_y[loop] <= (y[loop]>>>1 - test_vector_y[loop]);
+                comp_z[loop] <= (z[loop]>>>1 - test_vector_z[loop]);
             end
         end
     end
 
-endmodule
+endmodule

Example_CORDIC/Verilog Design/Verilog Codes/CORDIC_atan_test.v

@@ -0,0 +1,114 @@
+/***********************************************
+Module Name:   CORDIC_atan_test
+Feature:       Testbench for CORDIC (mode 2)
+               An example for the GEM Projects
+Coder:         Garfield
+Organization:  XXXX Group, Department of Architecture
+------------------------------------------------------
+Variables:
+         clk: clock for processing
+         reset: reset flag
+------------------------------------------------------
+History:
+06-21-2016: First Version by Garfield
+***********************************************/
+`timescale 10 ns/100 ps
+//Simulation time assignment
+`define MODE 2
+`define LENGTH 256
+`define WIDTH 16
+`define ORDER 12
+
+
+//Insert the modules
+module CORDIC_atan_test;
+
+//defination for Variables
+reg clk;
+reg reset;
+
+reg[7:0] cntr;
+//loop for test vectors
+
+reg signed[(`WIDTH-1):0] test_vector_tan[(`LENGTH-1):0];
+reg signed[(`WIDTH-1):0] test_vector_atan[(`LENGTH-1):0];
+//Test Vector Value
+
+wire signed[(`WIDTH-1):0] atan_value;
+//middle signals
+
+wire signed[(`WIDTH-1):0] atan_adj;
+wire signed[(`WIDTH-1):0] comp_atan;
+//Results right? Comparision results
+
+wire[(`WIDTH*2-1):0] op;
+wire[(`WIDTH*2-1):0] res;
+wire signed[(`WIDTH-1):0] res_atan;
+
+
+wire [7:0] index;
+
+assign res_atan = res[`WIDTH -1 : 0];
+
+assign op = {{(`WIDTH){1'b0}}, test_vector_tan[cntr]};
+
+assign index = (cntr - 1 - `ORDER) % `LENGTH;
+
+assign atan_value = test_vector_atan[index];
+
+assign atan_adj = res_atan;
+
+assign comp_atan = atan_value - atan_adj;
+
+//Connection to the modules
+CORDIC #(.MODE(`MODE))
+//CORDIC Mode
+ C  ( 
+    .CLK(clk), .RESET_n(reset),
+    .operand(op), .results(res)
+   );
+//Clock generation
+    initial
+    begin
+      clk = 0;
+      //Reset
+      forever  
+      begin
+           #10 clk = !clk;
+           //Reverse the clock in each 10ns
+      end
+    end
+
+//Reset operation
+    initial  
+    begin
+      reset = 0;
+      //Reset enable
+      #14  reset = 1;
+     //Counter starts
+    end
+
+//Load the test vectors
+    initial  
+    begin
+      $readmemh("tan_test_vector.txt", test_vector_tan);
+      $readmemh("atan_test_vector.txt", test_vector_atan);
+    end
+
+//Load the input of 0 order element
+
+//Comparision
+    always @(posedge clk or negedge reset)
+    begin
+        if ( !reset)
+        //reset statement: counter keeps at 0
+        begin
+            cntr <= 8'h00;
+        end
+        else
+        begin
+            cntr <= cntr + 8'h01;
+        end
+    end
+
+endmodule