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update multiplier docs for signed variants
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ganewto committed Dec 4, 2024
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15 changes: 8 additions & 7 deletions doc/components/multiplier.md
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ as two `Logic`s and adds the result to a third `Logic` with width
equal to the sum of the widths of the main inputs. Similar to the `Multiplier`,
the signs of the operands are either fixed by a parameter,
or runtime selectable, e.g.: `signedMultiplicand` or `selectSignedMultiplicand`.
The output of the multiplier also has a signal telling us if the result is to be
The output of the multiply-accumulate also has a signal telling us if the result is to be
treated as signed.

We have a
Expand All @@ -33,7 +33,7 @@ The compression tree based arithmetic units are built from a set of components f

## Carry Save Multiplier

Carry save multiplier is a digital circuit used for performing multiplication operations. It
The carry-save multiplier is a digital circuit used for performing multiplication operations. It
is particularly useful in applications that require high speed
multiplication, such as digital signal processing.

Expand All @@ -42,7 +42,8 @@ The
module in ROHD-HCL accept input parameters the clock `clk` signal,
reset `reset` signal, `Logic`s' a and b as the input pin and the name
of the module `name`. Note that the width of the inputs must be the
same or `RohdHclException` will be thrown.
same or `RohdHclException` will be thrown. The output latency is equal to the width of the inputs
given by `latency` on the component.

An example is shown below to multiply two inputs of signals that have 4-bits of width.

Expand Down Expand Up @@ -103,7 +104,7 @@ The parameters of the
- An optional `selectSignedMultiplier` control signal which overrides the `signedMultiplier` parameter allowing for runtime control of signed or unsigned operation with the same hardware. `signedMultiplier` must be false if using this control signal.
- An optional `clk`, as well as `enable` and `reset` that are used to add a pipestage in the `ColumnCompressor` to allow for pipelined operation.

Here is an example of use of the `CompressionTreeMultiplier`:
Here is an example of use of the `CompressionTreeMultiplier` with one signed input:

```dart
const widthA = 6;
Expand All @@ -116,7 +117,7 @@ Here is an example of use of the `CompressionTreeMultiplier`:
b.put(3);
final multiplier =
CompressionTreeMultiplier(a, b, radix, signed: true);
CompressionTreeMultiplier(a, b, radix, signedMultiplicand: true);
final product = multiplier.product;
Expand Down Expand Up @@ -145,7 +146,7 @@ The parameters of the
- An optional `selectSignedAddend` control signal which overrides the `signedAddend` parameter allowing for runtime control of signed or unsigned operation with the same hardware. `signedAddend` must be false if using this control signal.
- An optional `clk`, as well as `enable` and `reset` that are used to add a pipestage in the `ColumnCompressor` to allow for pipelined operation.

Here is an example of using the `CompressionTreeMultiplyAccumulate`:
Here is an example of using the `CompressionTreeMultiplyAccumulate` with all inputs as signed:

```dart
const widthA = 6;
Expand All @@ -159,7 +160,7 @@ Here is an example of using the `CompressionTreeMultiplyAccumulate`:
b.put(3);
c.put(5);
final multiplier = CompressionTreeMultiplyAccumulate(a, b, c, radix, signed: true);
final multiplier = CompressionTreeMultiplyAccumulate(a, b, c, radix, signedMultiplicand: true, signedMultiplier: true, signedAddend: true);
final accumulate = multiplier.accumulate;
Expand Down
8 changes: 4 additions & 4 deletions doc/components/multiplier_components.md
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ row slice mult

A few things to note: first, that we are negating by 1s complement (so we need a -0) and second, these rows do not add up to (18: 10010). For Booth encoded rows to add up properly, they need to be in 2s complement form, and they need to be sign-extended.

Here is the matrix with crude sign extension (this formatting is available from our `PartialProductGenerator` component). With 2s complementation, and sign bits folded in (note the LSB of each row has a sign term from the previous row), these addends are correctly formed and add to (18: 10010).
Here is the matrix with a crude sign extension `brute` (the table formatting is available from our `PartialProductGenerator` component). With 2s complementation, and sign bits folded in (note the LSB of each row has a sign term from the previous row), these addends are correctly formed and add to (18: 10010).

```text
7 6 5 4 3 2 1 0
Expand All @@ -64,7 +64,7 @@ A few things to note: first, that we are negating by 1s complement (so we need a
0 0 0 1 0 0 1 0 : 00010010 = 18 (18)
```

There are more compact ways of doing sign-extension which result in far fewer additions. Here is an example of compact sign-extension:
There are more compact ways of doing sign-extension which result in far fewer additions. Here is an example of `compact` sign-extension, where the last row which carries only a sign bit is folded into the previous row:

```text
7 6 5 4 3 2 1 0
Expand All @@ -86,7 +86,7 @@ And of course, with higher radix-encoding, we select more bits at a time from th
0 0 0 1 0 0 1 0 : 00010010 = 18 (18)
```

Note that radix-4 shifts by 2 positions each row, but with only two rows and with sign-extension adding an LSB bit, you only see a shift of 1 in row 1.
Note that radix-4 shifts by 2 positions each row, but with only two rows and with sign-extension adding an LSB bit to each row, you only see a shift of 1 in row 1, but in a larger example you would see the two-bit shift in the following rows.

## Partial Product Generator

Expand Down Expand Up @@ -222,7 +222,7 @@ Finally, we produce the product.

```dart
final pp =
PartialProductGeneratorCompactRectSignExtension(a, b, RadixEncoder(radix), signed: true);
PartialProductGeneratorCompactRectSignExtension(a, b, RadixEncoder(radix), signedMultiplicand: true, signedMultiplier: true);
final compressor = ColumnCompressor(pp)..compress();
final adder = ParallelPrefixAdder(
compressor.exractRow(0), compressor.extractRow(1), BrentKung.new);
Expand Down

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