add inital support for LNL (Lunar Lake)

Change-Id: I86f53f2e8fde44dd3431ad5c9df5bd91be534420
intel · Sep 16, 2024 · 0ad25bf · 0ad25bf
1 parent 61de596
commit 0ad25bf
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Showing 2 changed files with 16 additions and 1 deletion.
diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp
@@ -711,6 +711,7 @@ void PCM::initCStateSupportTables()
         case ADL:
         case RPL:
         case MTL:
+        case LNL:
         case SNOWRIDGE:
             PCM_CSTATE_ARRAY(pkgCStateMsr, PCM_PARAM_PROTECT({0, 0, 0x3F8, 0, 0x3F9, 0, 0x3FA, 0, 0, 0, 0 }) );
         case NEHALEM_EP:
@@ -785,6 +786,7 @@ void PCM::initCStateSupportTables()
         case ADL:
         case RPL:
         case MTL:
+        case LNL:
         case SNOWRIDGE:
         case ICX:
         case SPR:
@@ -1637,6 +1639,7 @@ bool PCM::detectNominalFrequency()
                || cpu_model == ADL
                || cpu_model == RPL
                || cpu_model == MTL
+               || cpu_model == LNL
                || cpu_model == SKX
                || cpu_model == ICX
                || cpu_model == SPR
@@ -3237,6 +3240,7 @@ bool PCM::isCPUModelSupported(const int model_)
             || model_ == ADL
             || model_ == RPL
             || model_ == MTL
+            || model_ == LNL
             || model_ == SKX
             || model_ == ICX
             || model_ == SPR
@@ -3408,7 +3412,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter
         canUsePerf = false;
         if (!silent) std::cerr << "Installed Linux kernel perf does not support hardware top-down level-1 counters. Using direct PMU programming instead.\n";
     }
-    if (canUsePerf && (cpu_model == ADL || cpu_model == RPL || cpu_model == MTL))
+    if (canUsePerf && (cpu_model == ADL || cpu_model == RPL || cpu_model == MTL || cpu_model == LNL))
     {
         canUsePerf = false;
         if (!silent) std::cerr << "Linux kernel perf rejects an architectural event on your platform. Using direct PMU programming instead.\n";
@@ -3495,6 +3499,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter
             case ADL:
             case RPL:
             case MTL:
+            case LNL:
                 LLCArchEventInit(hybridAtomEventDesc);
                 hybridAtomEventDesc[2].event_number = SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR;
                 hybridAtomEventDesc[2].umask_value = SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK;
@@ -4844,6 +4849,8 @@ const char * PCM::getUArchCodename(const int32 cpu_model_param) const
             return "Raptor Lake";
         case MTL:
             return "Meteor Lake";
+        case LNL:
+            return "Lunar Lake";
         case SKX:
             if (cpu_model_param >= 0)
             {

diff --git a/src/cpucounters.h b/src/cpucounters.h
@@ -1633,6 +1633,7 @@ class PCM_API PCM
             case ADL:
             case RPL:
             case MTL:
+            case LNL:
                 if (topology[coreID].core_type == TopologyEntry::Atom)
                 {
                     return std::make_pair(OFFCORE_RESPONSE_0_EVTNR, event + 1);
@@ -1648,6 +1649,7 @@ class PCM_API PCM
        case ADL: // ADL big core (GLC)
        case RPL:
        case MTL:
+       case LNL:
            useGLCOCREvent = true;
            break;
        }
@@ -1873,6 +1875,7 @@ class PCM_API PCM
         RPL_2 = 0xbf,
         RPL_3 = 0xbe,
         MTL = 0xAA,
+        LNL = 0xBD,
         BDX = 79,
         KNL = 87,
         SKL = 94,
@@ -2093,6 +2096,8 @@ class PCM_API PCM
         case RPL:
         case MTL:
             return 6;
+        case LNL:
+            return 12;
         case SNOWRIDGE:
             return 4;
         case DENVERTON:
@@ -2432,6 +2437,7 @@ class PCM_API PCM
                  || cpu_model == PCM::ADL
                  || cpu_model == PCM::RPL
                  || cpu_model == PCM::MTL
+                 || cpu_model == PCM::LNL
                  || cpu_model == PCM::SPR
                  || cpu_model == PCM::EMR
                  || cpu_model == PCM::SRF
@@ -4229,6 +4235,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType
         || cpu_model == PCM::ADL
         || cpu_model == PCM::RPL
         || cpu_model == PCM::MTL
+        || cpu_model == PCM::LNL
         ) {
         return after.Event[BasicCounterState::SKLL2MissPos] - before.Event[BasicCounterState::SKLL2MissPos];
     }
@@ -4340,6 +4347,7 @@ uint64 getL3CacheHitsSnoop(const CounterStateType & before, const CounterStateTy
         || cpu_model == PCM::ADL
         || cpu_model == PCM::RPL
         || cpu_model == PCM::MTL
+        || cpu_model == PCM::LNL
         )
     {
         const int64 misses = getL3CacheMisses(before, after);