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Might fix a gremlin issue where fractionaly synth config isn't set correctly without first being changed to an incorrect value.
cf. -Wint-in-bool-context
* md/master: (56 commits) fix warning time2ntp() catch exceptions travis-ci add bitinfo script oops minor add flashwrite safety cross-check of bit file header flash use fstream readout header of Xilinx bit stream file/rom doc evg: also check usecdiv during fracsynth config evg: fix seq trigger src init evm: fix FCT DC values evg add more UVIN sequence triggers update opis minor more clock control more fct more evgEvtClk consolidate with evgMrm missing ...
June 19 datasheet shows offset difference between MapRam1 and MapRam2 is 0x1000 not 0x2000
* krmpotic/patch-1: fix datasheet mismatch
shouldn't call exitWait() with locks held...
values confirmed with HW manufacturer
bits that are about to be set should be cleared
Works fine at 130 MHz.
This will help with separate building of the module
The RPM building part of this is RedHat specific, but the DKMS part allows the mrf-pci kernel module to be installed as a version independent standalone module.
This is a bit of a brute force rule and provides full access to all users.
Also allow group to be specified by editing local CONFIG file
at the moment, changing prescaler's Div-SP causes PhasOffs-CO_ to reset prescaler's phase-offset to 0 if user used PhasOffs:Raw-SP to set it. Fix this, by hanging Div-RB CPP on -RB not on -SP.
Reverse pull request
… community prefixes.
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docs: 2.3.1-beta release that is fully compatible with the community 2.3.