[bsp][stm32] add a new bsp for stm32h723-st-nucleo board

bsp/stm32/stm32h723-st-nucleo/.gitignore

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+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/stm32/stm32h723-st-nucleo/Kconfig

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+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+config SOC_STM32H723ZG
+    bool
+    select SOC_SERIES_STM32H7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+config BOARD_STM32H723_NUCLEO
+    bool
+    select BOARD_SERIES_STM32_NUCLEO_144
+    default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "board/Kconfig"
+endif

bsp/stm32/stm32h723-st-nucleo/README.md

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+# STM32H723-Nucleo BSP Introduction
+
+[中文](README_zh.md) 
+
+### Description
+
+STM32H723xE/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating-point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
+
+STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte of flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multilayer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).
+
+The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low-power comparators, a low-power RTC, four general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.
+
+### All features
+
+- Includes ST state-of-the-art patented technology
+- Core
+  - 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
+- Memories
+  - Up to 1 Mbyte of embedded flash memory with ECC
+  - SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real-time data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
+  - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
+  - 2 x Octo-SPI interface with XiP
+  - 2 x SD/SDIO/MMC interface
+  - Bootloader
+- Graphics
+  - Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
+  - LCD-TFT controller supporting up to XGA resolution
+- Clock, reset and supply management
+  - 1.62 V to 3.6 V application supply and I/O
+  - POR, PDR, PVD and BOR
+  - Dedicated USB power
+  - Embedded LDO regulator
+  - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
+  - External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
+- Low power
+  - Sleep, Stop and Standby modes
+  - VBAT supply for RTC, 32×32-bit backup registers
+- Analog
+  - 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in double-interleaved mode
+  - 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
+  - 2 x comparators
+  - 2 x operational amplifier GBW = 8 MHz
+  - 2× 12-bit D/A converters
+- Digital filters for sigma delta modulator (DFSDM)
+  - 8 channels/4 filters
+- 4 DMA controllers to offload the CPU
+  - 1 × MDMA with linked list support
+  - 2 × dual-port DMAs with FIFO
+  - 1 × basic DMA with request router capabilities
+- 24 timers
+  - Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
+  - 2x watchdogs, 1x SysTick timer
+- Debug mode
+  - SWD and JTAG interfaces
+  - 2-Kbyte embedded trace buffer
+
+- Up to 114 I/O ports with interrupt capability
+- Up to 35 communication interfaces
+  - Up to 5 × I2C FM+ interfaces (SMBus/PMBus™)
+  - Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART
+  - Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode)
+  - 2x SAI (serial audio interface)
+  - 1× FD/TT-CAN and 2x FD-CAN
+  - 8- to 14-bit camera interface
+  - 16-bit parallel slave synchronous interface
+  - SPDIF-IN interface
+  - HDMI-CEC
+  - Ethernet MAC interface with DMA controller
+  - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY
+  - SWPMI single-wire protocol master I/F
+  - MDIO slave interface
+- Mathematical acceleration
+  - CORDIC for trigonometric functions acceleration
+  - FMAC: Filter mathematical accelerator
+- Digital temperature sensor
+- True random number generator
+- CRC calculation unit
+- RTC with subsecond accuracy and hardware calendar
+- ROP, PC-ROP, tamper detection
+- 96-bit unique ID
+- All packages are ECOPACK2 compliant
+
+## Read more
+
+|                          Documents                           |                         Description                          |
+| :----------------------------------------------------------: | :----------------------------------------------------------: |
+| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) |
+| [STM32H723ZG ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html#documentation) |          STM32H723ZG datasheet and other resources           |
+
+## Maintained By
+
+[hywing](https://github.com/hywing)

bsp/stm32/stm32h723-st-nucleo/README_zh.md

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+# STM32H723-st-nucleo 开发板 BSP 说明
+
+## 简介
+
+本文档为 hywing为 STM32H723-st-nucleo 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+STM32H723 是 ST 推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 550Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H723 的芯片性能。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32H723，主频550MHz，1MB FLASH ，564K RAM
+- 常用接口：USB转串口、以太网接口、USB接口
+- 调试接口，标准 JTAG/SWD
+
+开发板更多详细信息请参考[STM32H723](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| USB 转串口        |     支持     |  
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | |
+| UART              |     支持     |   UART3                                   |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED循环点亮。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.0 build Dec  2 2024 11:35:30
+ 2006 - 2024 Copyright by RT-Thread team
+
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 调试串口为串口3 映射说明
+
+    PD8     ------> USART3_TX
+
+    PD9     ------> USART3_RX 
+
+## 联系人信息
+
+维护人:
+
+-  [hywing](https://github.com/hywing)

bsp/stm32/stm32h723-st-nucleo/SConscript

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+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32h723-st-nucleo/SConstruct

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+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32H7xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/stm32/stm32h723-st-nucleo/applications/SConscript

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+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')