fix: clock mux for cpu

hpmicro · Jun 14, 2024 · d1b34c7 · d1b34c7
1 parent 48830f3
commit d1b34c7
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diff --git a/data/registers/sysctl_v53.yaml b/data/registers/sysctl_v53.yaml
@@ -313,6 +313,7 @@ fieldset/CLOCK_CPU:
       description: current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3.
       bit_offset: 8
       bit_size: 3
+      enum: CLOCK_MUX
     - name: SUB0_DIV
       description: "ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …."
       bit_offset: 16

diff --git a/data/registers/sysctl_v62.yaml b/data/registers/sysctl_v62.yaml
@@ -335,6 +335,7 @@ fieldset/CLOCK_CPU:
       description: current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll2_clk0 7:pll2_clk1.
       bit_offset: 8
       bit_size: 3
+      enum: CLOCK_MUX
     - name: SUB0_DIV
       description: "axi bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …."
       bit_offset: 16

diff --git a/data/registers/sysctl_v63.yaml b/data/registers/sysctl_v63.yaml
@@ -316,6 +316,7 @@ fieldset/CLOCK_CPU:
       description: current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll2_clk0 7:pll2_clk1.
       bit_offset: 8
       bit_size: 4
+      enum: CLOCK_MUX
     - name: SUB0_DIV
       description: "axi bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …."
       bit_offset: 16