RISC-V support MVP

Cargo.toml

@@ -35,6 +35,8 @@ instrument = ["rftrace", "rftrace-frontend"]
 gdbstub = { git = "https://github.com/daniel5151/gdbstub", branch = "dev/0.6" }
 gdbstub_arch = { git = "https://github.com/daniel5151/gdbstub", branch = "dev/0.6" }
 x86_64 = { git = "https://github.com/mkroening/x86_64", branch = "debug-stable" }
+kvm-bindings = { git = "https://github.com/simonschoening/kvm-bindings", branch = "riscv" }
+kvm-ioctls = { git = "https://github.com/simonschoening/kvm-ioctls", branch = "riscv" }
 
 [dependencies]
 bitflags = "1.3"
@@ -47,21 +49,19 @@ env_logger = "0.9"
 envmnt = "0.9"
 gdbstub = "0.5"
 gdbstub_arch = "0.1.0"
-goblin = { version = "0.4", default-features = false, features = ["elf64", "elf32", "endian_fd", "std"] }
+goblin = { version = "0.4.3", default-features = false, features = ["elf64", "elf32", "endian_fd", "std"] }
 lazy_static = "1.4"
 libc = "0.2"
 log = "0.4"
-raw-cpuid = "10.2"
 rustc-serialize = "0.3"
 thiserror = "1.0"
-x86_64 = "0.14"
 
 rftrace = { version = "0.1", optional = true }
 rftrace-frontend = { version = "0.1", optional = true }
 
 [target.'cfg(target_os = "linux")'.dependencies]
 kvm-bindings = "0.5"
-kvm-ioctls = "0.10"
+kvm-ioctls = "0.11.0"
 mac_address = "1.1"
 nix = "0.23"
 tun-tap = { version = "0.1", default-features = false }
@@ -75,6 +75,9 @@ xhypervisor = "0.0"
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 x86_64 = { version = "0.14", default-features = false }
 
+[target.'cfg(target_arch = "x86_64")'.dependencies.raw-cpuid]
+version = "10.2.0"
+
 [target.'cfg(all(target_arch = "x86_64", target_os = "macos"))'.dependencies]
 x86 = { version = "0.43", default-features = false }
 

src/bin/uhyve.rs

@@ -69,7 +69,7 @@ fn main() {
 		.arg(
 			Arg::with_name("DISABLE_HUGEPAGE")
 				.long("disable-hugepages")
-				.help("Disable the usage of huge pages"),
+				.help("Disable the usage of transparent huge pages"),
 		)
 		.arg(
 			Arg::with_name("MERGEABLE")
@@ -116,6 +116,13 @@ fn main() {
 				.takes_value(true)
 				.env("HERMIT_GDB_PORT"),
 		)
+		.arg(
+			Arg::with_name("HUGETLBFS")
+				.long("hugetlbfs")
+				.value_name("HUGETLBFS")
+				.help("Hugetlbfs path")
+				.takes_value(true),
+		)
 		.arg(
 			Arg::with_name("NETIF")
 				.long("nic")
@@ -241,6 +248,7 @@ fn main() {
 	if matches.is_present("VERBOSE") {
 		verbose = true;
 	}
+	#[cfg(target_arch = "x86_64")]
 	let gdbport = matches
 		.value_of("GDB_PORT")
 		.map(|p| p.parse::<u16>().expect("Could not parse gdb port"))
@@ -249,13 +257,18 @@ fn main() {
 				.ok()
 				.map(|p| p.parse::<u16>().expect("Could not parse gdb port"))
 		});
+	#[cfg(target_arch = "riscv64")]
+	let gdbport = None;
+
+	let hugetlbfs_path = matches.value_of("HUGETLBFS");
 
 	let params = vm::Parameter {
 		mem_size,
 		num_cpus,
 		verbose,
 		hugepage,
 		mergeable,
+		hugetlbfs_path,
 		ip,
 		gateway,
 		mask,

src/linux/arch/mod.rs

@@ -0,0 +1,11 @@
+#[cfg(target_arch = "x86_64")]
+pub mod x86_64;
+
+#[cfg(target_arch = "riscv64")]
+pub mod riscv;
+
+#[cfg(target_arch = "x86_64")]
+pub use self::x86_64::vcpu;
+
+#[cfg(target_arch = "riscv64")]
+pub use self::riscv::vcpu;

src/linux/arch/riscv/consts.rs

@@ -0,0 +1,110 @@
+use kvm_bindings::*;
+
+pub const SBI_CONSOLE_PUTCHAR: u64 = 0x01;
+pub const SBI_CONSOLE_GETCHAR: u64 = 0x02;
+
+#[cfg(target_arch = "riscv32")]
+const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U32;
+
+#[cfg(target_arch = "riscv64")]
+const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U64;
+
+pub const KVM_REG_RISCV_CONFIG_ISA: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CONFIG as u64 | KVM_REG_SIZE_ULONG | 0x00;
+
+pub const KVM_REG_RISCV_CORE_PC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x00;
+pub const KVM_REG_RISCV_CORE_RA: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x01;
+pub const KVM_REG_RISCV_CORE_SP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x02;
+pub const KVM_REG_RISCV_CORE_GP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x03;
+pub const KVM_REG_RISCV_CORE_TP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x04;
+pub const KVM_REG_RISCV_CORE_T0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x05;
+pub const KVM_REG_RISCV_CORE_T1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x06;
+pub const KVM_REG_RISCV_CORE_T2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x07;
+pub const KVM_REG_RISCV_CORE_S0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x08;
+pub const KVM_REG_RISCV_CORE_S1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x09;
+pub const KVM_REG_RISCV_CORE_A0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0a;
+pub const KVM_REG_RISCV_CORE_A1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0b;
+pub const KVM_REG_RISCV_CORE_A2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0c;
+pub const KVM_REG_RISCV_CORE_A3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0d;
+pub const KVM_REG_RISCV_CORE_A4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0e;
+pub const KVM_REG_RISCV_CORE_A5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0f;
+pub const KVM_REG_RISCV_CORE_A6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x10;
+pub const KVM_REG_RISCV_CORE_A7: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x11;
+pub const KVM_REG_RISCV_CORE_S2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x12;
+pub const KVM_REG_RISCV_CORE_S3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x13;
+pub const KVM_REG_RISCV_CORE_S4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x14;
+pub const KVM_REG_RISCV_CORE_S5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x15;
+pub const KVM_REG_RISCV_CORE_S6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x16;
+pub const KVM_REG_RISCV_CORE_S7: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x17;
+pub const KVM_REG_RISCV_CORE_S8: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x18;
+pub const KVM_REG_RISCV_CORE_S9: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x19;
+pub const KVM_REG_RISCV_CORE_S10: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1a;
+pub const KVM_REG_RISCV_CORE_S11: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1b;
+pub const KVM_REG_RISCV_CORE_T3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1c;
+pub const KVM_REG_RISCV_CORE_T4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1d;
+pub const KVM_REG_RISCV_CORE_T5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1e;
+pub const KVM_REG_RISCV_CORE_T6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1f;
+pub const KVM_REG_RISCV_CORE_MODE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x20;
+
+pub const KVM_REG_RISCV_CSR_SSTATUS: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x00;
+pub const KVM_REG_RISCV_CSR_SIE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x01;
+pub const KVM_REG_RISCV_CSR_STVEC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x02;
+pub const KVM_REG_RISCV_CSR_SSCRATCH: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x03;
+pub const KVM_REG_RISCV_CSR_SEPC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x04;
+pub const KVM_REG_RISCV_CSR_SCAUSE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x05;
+pub const KVM_REG_RISCV_CSR_STVAL: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x06;
+pub const KVM_REG_RISCV_CSR_SIP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x07;
+pub const KVM_REG_RISCV_CSR_SATP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x08;
+
+pub const KVM_REG_RISCV_TIMER_FREQUENCY: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x00;
+pub const KVM_REG_RISCV_TIMER_TIME: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x01;
+pub const KVM_REG_RISCV_TIMER_COMPARE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x02;
+pub const KVM_REG_RISCV_TIMER_STATE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x03;
+
+//TODO: RISC-V F-extension registers, RISC-V D-extension registers

src/linux/arch/riscv/mod.rs

@@ -0,0 +1,3 @@
+pub mod consts;
+/// Arch riscv
+pub mod vcpu;