Fix fmt

hermit-os · Dec 9, 2021 · f8acbfd · f8acbfd
1 parent 6661326
commit f8acbfd
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Showing 10 changed files with 168 additions and 115 deletions.
diff --git a/src/bin/uhyve.rs b/src/bin/uhyve.rs
@@ -261,7 +261,7 @@ fn main() {
 	let gdbport = None;
 
 	let hugetlbfs_path = matches.value_of("HUGETLBFS");
-	
+
 	let params = vm::Parameter {
 		mem_size,
 		num_cpus,

diff --git a/src/linux/arch/mod.rs b/src/linux/arch/mod.rs
@@ -5,11 +5,7 @@ pub mod x86_64;
 pub mod riscv;
 
 #[cfg(target_arch = "x86_64")]
-pub use {
-    self::x86_64::vcpu,
-};
+pub use self::x86_64::vcpu;
 
 #[cfg(target_arch = "riscv64")]
-pub use {
-    self::riscv::vcpu,
-};
+pub use self::riscv::vcpu;
diff --git a/src/linux/arch/riscv/consts.rs b/src/linux/arch/riscv/consts.rs
@@ -9,55 +9,102 @@ const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U32;
 #[cfg(target_arch = "riscv64")]
 const KVM_REG_SIZE_ULONG: u64 = KVM_REG_SIZE_U64;
 
-pub const KVM_REG_RISCV_CONFIG_ISA: u64 = KVM_REG_RISCV as u64| KVM_REG_RISCV_CONFIG as u64 | KVM_REG_SIZE_ULONG | 0x00;
-
-pub const KVM_REG_RISCV_CORE_PC: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x00;
-pub const KVM_REG_RISCV_CORE_RA: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x01;
-pub const KVM_REG_RISCV_CORE_SP: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x02;
-pub const KVM_REG_RISCV_CORE_GP: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x03;
-pub const KVM_REG_RISCV_CORE_TP: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x04;
-pub const KVM_REG_RISCV_CORE_T0: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x05;
-pub const KVM_REG_RISCV_CORE_T1: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x06;
-pub const KVM_REG_RISCV_CORE_T2: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x07;
-pub const KVM_REG_RISCV_CORE_S0: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x08;
-pub const KVM_REG_RISCV_CORE_S1: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x09;
-pub const KVM_REG_RISCV_CORE_A0: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0a;
-pub const KVM_REG_RISCV_CORE_A1: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0b;
-pub const KVM_REG_RISCV_CORE_A2: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0c;
-pub const KVM_REG_RISCV_CORE_A3: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0d;
-pub const KVM_REG_RISCV_CORE_A4: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0e;
-pub const KVM_REG_RISCV_CORE_A5: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0f;
-pub const KVM_REG_RISCV_CORE_A6: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x10;
-pub const KVM_REG_RISCV_CORE_A7: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x11;
-pub const KVM_REG_RISCV_CORE_S2: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x12;
-pub const KVM_REG_RISCV_CORE_S3: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x13;
-pub const KVM_REG_RISCV_CORE_S4: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x14;
-pub const KVM_REG_RISCV_CORE_S5: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x15;
-pub const KVM_REG_RISCV_CORE_S6: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x16;
-pub const KVM_REG_RISCV_CORE_S7: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x17;
-pub const KVM_REG_RISCV_CORE_S8: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x18;
-pub const KVM_REG_RISCV_CORE_S9: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x19;
-pub const KVM_REG_RISCV_CORE_S10: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1a;
-pub const KVM_REG_RISCV_CORE_S11: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1b;
-pub const KVM_REG_RISCV_CORE_T3: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1c;
-pub const KVM_REG_RISCV_CORE_T4: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1d;
-pub const KVM_REG_RISCV_CORE_T5: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1e;
-pub const KVM_REG_RISCV_CORE_T6: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1f;
-pub const KVM_REG_RISCV_CORE_MODE: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x20;
-
-pub const KVM_REG_RISCV_CSR_SSTATUS: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x00;
-pub const KVM_REG_RISCV_CSR_SIE: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x01;
-pub const KVM_REG_RISCV_CSR_STVEC: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x02;
-pub const KVM_REG_RISCV_CSR_SSCRATCH: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x03;
-pub const KVM_REG_RISCV_CSR_SEPC: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x04;
-pub const KVM_REG_RISCV_CSR_SCAUSE: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x05;
-pub const KVM_REG_RISCV_CSR_STVAL: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x06;
-pub const KVM_REG_RISCV_CSR_SIP: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x07;
-pub const KVM_REG_RISCV_CSR_SATP: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x08;
-
-pub const KVM_REG_RISCV_TIMER_FREQUENCY: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x00;
-pub const KVM_REG_RISCV_TIMER_TIME: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x01;
-pub const KVM_REG_RISCV_TIMER_COMPARE: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x02;
-pub const KVM_REG_RISCV_TIMER_STATE: u64 = KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x03;
-
-//TODO: RISC-V F-extension registers, RISC-V D-extension registers
+pub const KVM_REG_RISCV_CONFIG_ISA: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CONFIG as u64 | KVM_REG_SIZE_ULONG | 0x00;
+
+pub const KVM_REG_RISCV_CORE_PC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x00;
+pub const KVM_REG_RISCV_CORE_RA: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x01;
+pub const KVM_REG_RISCV_CORE_SP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x02;
+pub const KVM_REG_RISCV_CORE_GP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x03;
+pub const KVM_REG_RISCV_CORE_TP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x04;
+pub const KVM_REG_RISCV_CORE_T0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x05;
+pub const KVM_REG_RISCV_CORE_T1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x06;
+pub const KVM_REG_RISCV_CORE_T2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x07;
+pub const KVM_REG_RISCV_CORE_S0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x08;
+pub const KVM_REG_RISCV_CORE_S1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x09;
+pub const KVM_REG_RISCV_CORE_A0: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0a;
+pub const KVM_REG_RISCV_CORE_A1: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0b;
+pub const KVM_REG_RISCV_CORE_A2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0c;
+pub const KVM_REG_RISCV_CORE_A3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0d;
+pub const KVM_REG_RISCV_CORE_A4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0e;
+pub const KVM_REG_RISCV_CORE_A5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x0f;
+pub const KVM_REG_RISCV_CORE_A6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x10;
+pub const KVM_REG_RISCV_CORE_A7: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x11;
+pub const KVM_REG_RISCV_CORE_S2: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x12;
+pub const KVM_REG_RISCV_CORE_S3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x13;
+pub const KVM_REG_RISCV_CORE_S4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x14;
+pub const KVM_REG_RISCV_CORE_S5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x15;
+pub const KVM_REG_RISCV_CORE_S6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x16;
+pub const KVM_REG_RISCV_CORE_S7: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x17;
+pub const KVM_REG_RISCV_CORE_S8: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x18;
+pub const KVM_REG_RISCV_CORE_S9: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x19;
+pub const KVM_REG_RISCV_CORE_S10: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1a;
+pub const KVM_REG_RISCV_CORE_S11: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1b;
+pub const KVM_REG_RISCV_CORE_T3: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1c;
+pub const KVM_REG_RISCV_CORE_T4: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1d;
+pub const KVM_REG_RISCV_CORE_T5: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1e;
+pub const KVM_REG_RISCV_CORE_T6: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x1f;
+pub const KVM_REG_RISCV_CORE_MODE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CORE as u64 | KVM_REG_SIZE_ULONG | 0x20;
+
+pub const KVM_REG_RISCV_CSR_SSTATUS: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x00;
+pub const KVM_REG_RISCV_CSR_SIE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x01;
+pub const KVM_REG_RISCV_CSR_STVEC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x02;
+pub const KVM_REG_RISCV_CSR_SSCRATCH: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x03;
+pub const KVM_REG_RISCV_CSR_SEPC: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x04;
+pub const KVM_REG_RISCV_CSR_SCAUSE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x05;
+pub const KVM_REG_RISCV_CSR_STVAL: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x06;
+pub const KVM_REG_RISCV_CSR_SIP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x07;
+pub const KVM_REG_RISCV_CSR_SATP: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_CSR as u64 | KVM_REG_SIZE_ULONG | 0x08;
+
+pub const KVM_REG_RISCV_TIMER_FREQUENCY: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x00;
+pub const KVM_REG_RISCV_TIMER_TIME: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x01;
+pub const KVM_REG_RISCV_TIMER_COMPARE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x02;
+pub const KVM_REG_RISCV_TIMER_STATE: u64 =
+	KVM_REG_RISCV as u64 | KVM_REG_RISCV_TIMER as u64 | KVM_REG_SIZE_U64 | 0x03;
+
+//TODO: RISC-V F-extension registers, RISC-V D-extension registers
diff --git a/src/linux/arch/riscv/mod.rs b/src/linux/arch/riscv/mod.rs
@@ -1,4 +1,3 @@
+pub mod consts;
 /// Arch riscv
-
 pub mod vcpu;
-pub mod consts;
diff --git a/src/linux/arch/riscv/vcpu.rs b/src/linux/arch/riscv/vcpu.rs
@@ -1,15 +1,15 @@
 use crate::consts::*;
+use crate::linux::arch::riscv::consts::*;
 use crate::vm::HypervisorResult;
 use crate::vm::VcpuStopReason;
-use crate::vm::{VirtualCPU, BootInfo};
-use crate::linux::arch::riscv::consts::*;
+use crate::vm::{BootInfo, VirtualCPU};
 use kvm_bindings::*;
 use kvm_ioctls::{VcpuExit, VcpuFd};
+use std::cell::RefCell;
 use std::path::Path;
 use std::path::PathBuf;
 use std::ptr::write;
 use std::slice;
-use std::cell::RefCell;
 
 thread_local!(static SBI_UTF_BUFFER: RefCell<Vec<u8>> = RefCell::new(Vec::new()));
 pub struct UhyveCPU {
@@ -25,12 +25,7 @@ impl UhyveCPU {
 		slice::from_raw_parts_mut(host as *mut u8, len)
 	}
 
-	pub fn new(
-		id: u32,
-		kernel_path: PathBuf,
-		vcpu: VcpuFd,
-		vm_start: usize,
-	) -> UhyveCPU {
+	pub fn new(id: u32, kernel_path: PathBuf, vcpu: VcpuFd, vm_start: usize) -> UhyveCPU {
 		UhyveCPU {
 			id,
 			vcpu,
@@ -57,19 +52,33 @@ impl VirtualCPU for UhyveCPU {
 
 		self.vcpu.set_mp_state(mp_state)?;
 
-		self.vcpu.set_one_reg(KVM_REG_RISCV_CORE_PC, entry_point)
-            .expect("Failed to set pc register");
+		self.vcpu
+			.set_one_reg(KVM_REG_RISCV_CORE_PC, entry_point)
+			.expect("Failed to set pc register");
 
-		let isa = self.vcpu.get_one_reg(KVM_REG_RISCV_CONFIG_ISA).expect("Failed to read ISA!");
+		let isa = self
+			.vcpu
+			.get_one_reg(KVM_REG_RISCV_CONFIG_ISA)
+			.expect("Failed to read ISA!");
 		debug!("Detected ISA {:X}", isa);
-		let timebase_freq = self.vcpu.get_one_reg(KVM_REG_RISCV_TIMER_FREQUENCY).expect("Failed to read timebase freq!");
+		let timebase_freq = self
+			.vcpu
+			.get_one_reg(KVM_REG_RISCV_TIMER_FREQUENCY)
+			.expect("Failed to read timebase freq!");
 		debug!("Detected a timebase frequency of {} Hz", timebase_freq);
-		unsafe {write(&mut (*(boot_info as *mut BootInfo)).timebase_freq, timebase_freq)};
+		unsafe {
+			write(
+				&mut (*(boot_info as *mut BootInfo)).timebase_freq,
+				timebase_freq,
+			)
+		};
 
-		self.vcpu.set_one_reg(KVM_REG_RISCV_CORE_A0, self.id as u64)
+		self.vcpu
+			.set_one_reg(KVM_REG_RISCV_CORE_A0, self.id as u64)
 			.expect("Failed to set a0 register");
 
-		self.vcpu.set_one_reg(KVM_REG_RISCV_CORE_A1, BOOT_INFO_ADDR)
+		self.vcpu
+			.set_one_reg(KVM_REG_RISCV_CORE_A1, BOOT_INFO_ADDR)
 			.expect("Failed to set a1 register");
 
 		Ok(())
@@ -117,19 +126,16 @@ impl VirtualCPU for UhyveCPU {
 								self.uart(c.unwrap().to_string())
 									.expect("UART failed"); */
 							}
-							_ => info!("Unhandled SBI call: {:?}", sbi_reason)
+							_ => info!("Unhandled SBI call: {:?}", sbi_reason),
 						}
-
 					}
-					VcpuExit::SystemEvent(ev_type, ev_flags) => {
-						match ev_type{
-							KVM_SYSTEM_EVENT_SHUTDOWN => {
-								debug!("Shutdown Exit, flags: {}", ev_flags);
-								return Ok(VcpuStopReason::Exit(0));
-							}
-							_ => info!("Unhandled SystemEvent: {}", ev_type)
+					VcpuExit::SystemEvent(ev_type, ev_flags) => match ev_type {
+						KVM_SYSTEM_EVENT_SHUTDOWN => {
+							debug!("Shutdown Exit, flags: {}", ev_flags);
+							return Ok(VcpuStopReason::Exit(0));
 						}
-					}
+						_ => info!("Unhandled SystemEvent: {}", ev_type),
+					},
 					VcpuExit::InternalError => {
 						panic!("{:?}", VcpuExit::InternalError)
 					}
@@ -174,7 +180,6 @@ impl Drop for UhyveCPU {
 	}
 }
 
-
 #[derive(Default, Debug)]
 pub struct Registers {
 	// Gotten from gnu-binutils/gdb/riscv-tdep.c
@@ -253,4 +258,4 @@ impl Registers {
 
 		registers
 	}
-}
+}
diff --git a/src/linux/arch/x86_64/mod.rs b/src/linux/arch/x86_64/mod.rs
@@ -1,3 +1,2 @@
 /// Arch x86_64
-
-pub mod vcpu;
+pub mod vcpu;
diff --git a/src/linux/mod.rs b/src/linux/mod.rs
@@ -32,11 +32,8 @@ use nix::sys::{
 	signal::{signal, SigHandler, Signal},
 };
 
-
 #[cfg(target_arch = "x86_64")]
-use crate::{
-	linux::gdb::{GdbUhyve, UhyveGdbEventLoop},
-};
+use crate::linux::gdb::{GdbUhyve, UhyveGdbEventLoop};
 
 use crate::{
 	vm::{VirtualCPU, Vm},